Defect detection using multiple sensors and parallel processing

• US 7,221,992 B2
• Filed: 10/13/2005
• Issued: 05/22/2007
• Est. Priority Date: 02/03/2003
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Smith, James A., Johnson, Erik
• Primary Examiner(s): Picard; Leo
• Assistant Examiner(s): SHECHTMAN, SEAN P
• Application Number:
  US11/250,799
• Publication Number:
  US 20060069460A1
• Time in Patent Office: 586 Days
• Field of Search: 700 1- 4, 700/19, 700/20, 700/51, 700/59, 700/90, 700/95, 700/96, 700/108, 700/109, 700/110, 700/112, 700/117, 438 5- 18, 709/200
• US Class Current: 700/110
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G06T 2207/10061 from scanning electron microscope
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Techniques for detecting defects on semiconductor wafers are described. The techniques involve a parallel processing system wherein a data distribution system contains data distribution nodes that are interconnected by multiple data transfer paths. This configuration allows data collected by any of the detectors to be routed to any one of a plurality of processing nodes. This in turn allows a variety of defect analysis algorithms to be implemented.

Claims

1. A computer-implemented method of detecting features on a semiconductor wafer comprising:

collecting data with a plurality of detectors that are positioned about the semiconductor wafer, wherein at least one of the detectors is configured to obtain data in a different manner from other detectors of the plurality of detectors, and wherein each detector collects one data frame for each of a plurality of device areas;

transmitting the data frames from each detector to a data distribution node, which is part of a set of data distribution nodes and wherein each data distribution node comprises a plurality of image buffers configured to hold the data frames and wherein the image buffers are logically separated from each other;

transferring a first data frame along a first data transfer path that connects a first and a second data distribution node;

transferring a second data frame along a second data transfer path that connects the first and second data distribution nodes;

routing the data frames from the data distribution nodes to processing nodes, wherein the data frames in the data distribution nodes are accessible by the processing nodes as read only data and wherein the transferring of data frames between data distribution nodes allows data from any one of the detectors to be routed to any one of the processing nodes;

processing the data frames within each of the processing nodes by analyzing the data frames in order to obtain defect information.

2. A computer-implemented method as recited in claim 1 wherein a number of data transfer paths equals the number of detectors that is used to collect data.

3. A computer-implemented method as recited in claim 1 wherein each detector collects data for each of three or more device areas.

4. A computer-implemented method as recited in claim 1 wherein the processing of data further comprises a composite-column based analysis that involves,

generating a set of first of data frames for each device area with each detector;

combining the data frames collected by each detector to generate a first composite image for each detector; and

comparing each data frame collected with a detector with the first composite image associated with that detector in a row based analysis in order to obtain defect information.

5. A computer-implemented method as recited in claim 4 wherein the processing of data further comprises collecting each of the first composite images from each detector;

and comparing the first composite images from each detector with each other in a composite row based analysis in order to obtain defect information.

6. A computer-implemented method as recited in claim 5 wherein the processing of data further comprises

combining, the data frames collected by each of the plurality of detectors for that device area to generate a set of third composite images, one for each device area;

and

comparing each third composite image with each other to obtain defect information.

7. A computer-implemented method as recited in claim 1 wherein the processing of data further comprises

generating a set of data frames for each device area, the set comprising one data frame for each detector;

comparing each data frame of the set data frames collected for a device area with the other data frames of the set in order to obtain defect information.

8. The method of claim 1 wherein obtaining data in a different manner from other detectors includes obtaining data frames from at least two different types of inspection devices.

9. The method of claim 1 wherein obtaining data in a different manner from other detectors comprises collecting the data frames using similar devices and wherein processing the data frames within each of the processing nodes includes processing the data frames includes using different data processing methodologies.

10. The method of claim 1 wherein processing the data frames within each of the processing nodes further includes enabling the alteration of analysis and testing parameters during operation of the computer-implemented method enabling on the fly adjustment of image processing and analysis.

11. A semiconductor wafer inspection system comprising:

a semiconductor wafer having a plurality of device areas;

a plurality of detectors positioned about a semiconductor wafer wherein each detector is configured to collect a data frame for each of the plurality of device areas, wherein at least one of the detectors is configured to obtain data a different manner from other detectors of the plurality of detectors wherein each data frame is configured to overlap adjacent data frames;

a data distribution system that includes,

a) a plurality of data distribution nodes each having,

a plurality of memory devices that are logically separated from each other and configured such that each memory device is configured to receive data frames from a specific detector of the plurality of detectors, and

processing node interfaces configured to facilitate transfer of data frames from memory devices to an associated processing node wherein the data frames are accessible to the associated processing node as read only information thereby ensuring memory coherency,

b) a plurality of data transfer paths connecting each of the data distribution nodes wherein each data transfer path transfers data frames collected by a respective detector;

a plurality of processing nodes configured to receive data frames from the processing node interfaces of the data distribution system, the processing nodes configured to analyze the data frames,

wherein the data transfer paths allow data frames collected by any one of the detectors to be routed to any one of the processing nodes; and

wherein each of the processing nodes are configured to perform data frame analysis in order to obtain defect information.

12. A semiconductor wafer inspection system as recited in claim 11 wherein each data distribution node includes a data buffer for the data frames collected by each of the detectors.

13. A semiconductor wafer inspection system as recited in claim 11 wherein each detector is configured to collect data from three or more device areas.

14. The semiconductor wafer inspection system of claim 11 wherein each detector collects a data frame corresponding to a same device area on the wafer;

and wherein the data frames are received by the processing nodes which are configured to perform a column based analysis of each of the data frames collected for each device area to obtain defect information.

15. The semiconductor wafer inspection system of claim 14 wherein the collected data frames corresponding to the same device area on the wafer are processed together as a combined image by the processing nodes to obtain defect information.

16. The semiconductor wafer inspection system of claim 15 wherein each of the combined images for each device area are compared against each other by the processing nodes in a composite column based analysis to obtain defect information.

17. The semiconductor wafer inspection system of claim 16 wherein each detector collects a plurality of data frames, wherein each data frame collected by a detector corresponds to one of a plurality of device areas on the wafer;

and wherein the data frames are received by the processing nodes which are configured to perform a row based analysis of each of the data frames to obtain defect information.

18. The semiconductor wafer inspection system of claim 17 wherein each detector collects a plurality of data frames wherein each data frame corresponds to a different device area, the data frames for each sensor are then processed by the processing nodes in a row based analysis that generate combined row images that are compared against individual data frames to obtain defect information.

19. The semiconductor wafer inspection system of claim 18 wherein the processing nodes process the combined row images in a composite row based analysis to obtain defect information.

20. The semiconductor wafer inspection system of claim 11 further including a central processor enabling control of the system and in particular enabling the alteration of analysis and testing parameters during operation of the system enabling on the fly adjustment of image processing and analysis.

21. A semiconductor wafer inspection system comprising:

a semiconductor wafer having a plurality of device areas;

a plurality of detectors positioned about a semiconductor wafer wherein each detector is configured to collect a data frame for each of the plurality of device areas, wherein each data frame is configured to overlap adjacent data frames;

a data distribution system that includes,

a) a plurality of data distribution nodes each having,

a plurality of memory devices that are logically separated from each other and configured such that each memory device is configured to receive data frames from a specific detector of the plurality of detectors, and

processing node interfaces configured to facilitate transfer of data frames from memory devices to an associated processing node wherein the data frames are accessible to the associated processing node as read only information thereby ensuring memory coherency,

b) a plurality of data transfer paths connecting each of the data distribution nodes wherein each data transfer path transfers data frames collected by a respective detector;

a plurality of processing nodes configured to receive data frames from the processing node interfaces of the data distribution system, the processing nodes configured to analyze the data frames,

wherein the data transfer paths allow data frames collected by any one of the detectors to be routed to any one of the processing nodes; and

wherein each of the processing nodes are configured to perform data frame analysis that includes processing the data frames using different data processing methodologies and then comparing data frames in order to obtain defect information.