Equipment for and method of detecting faults in semiconductor integrated circuits

• US 7,222,026 B2
• Filed: 03/28/2002
• Issued: 05/22/2007
• Est. Priority Date: 03/29/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ushiku, Yukihiro, Mitsutake, Kunihiro, Matsushita, Hiroshi
• Primary Examiner(s): Barlow; John
• Assistant Examiner(s): BHAT, ADITYA S
• Application Number:
  US10/107,297
• Publication Number:
  US 20030011376A1
• Time in Patent Office: 1,881 Days
• Field of Search: 702/35, 702/84, 702/182, 702/184, 382/149, 700/110
• US Class Current: 702/35
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An equipment for detecting faults in semiconductor integrated circuits includes a fault input unit to input fault information for the integrated circuits formed on a semiconductor wafer, a superimposing unit to superimpose the fault information with repeating units within the surface of the semiconductor wafer, and a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which faults are repeated every repeating unit.

Claims

1. An equipment for detecting faults in semiconductor integrated circuits comprising:

a fault input unit to input fault information for a plurality of divisional units on a surface of said semiconductor integrated circuits formed on a semiconductor wafer;

a superimposing unit providing superimposed fault information, including said fault information from said plurality of divisional units;

a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which a fault of one of said plurality of divisional units is repeated within another of said plurality of divisional units from said superimposed fault information; and

a clustering factor calculation unit to calculate a second characteristic factor representing a degree of polarization in a fault distribution within said semiconductor surface;

wherein said first characteristic factor calculation unit determines whether said faults are detected with said second characteristic factor but not detected with said first characteristic factor.

2. The equipment of claim 1, further comprising an abnormal region removal unit to delete abnormal fault information from said fault information before providing superimposed fault information.

3. The equipment of claim 1, further comprising an abnormal region removal unit to determine abnormal fault information, when a total of said fault information of a first one of the plurality of divisional units is greater than the fault information of each of the plurality of divisional units surrounding the first one of the plurality of divisional units.

4. The equipment of claim 2, wherein said abnormal region removal unit determines said abnormal fault information, when a total of said fault information of a first one of the plurality of divisional units is greater than the fault information of each of the plurality of divisional units surrounding the first one of the plurality of divisional units.

5. The equipment of claim 1, wherein said first characteristic factor calculation unit determines from said superimposed fault information whether said fault is repeated by comparing said first characteristic factor with a predetermined threshold value.

6. The equipment of claim 1, wherein the first characteristic factor shows a degree to which a plurality of faults of one of said plurality of divisional units are repeated within another of said plurality of divisional units from said superimposed fault information.