Programmable processor and method for matched aligned and unaligned storage instructions
DCFirst Claim
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1. A programmable processor comprising:
- a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file coupled to the data path and containing a plurality of registers; and
an execution unit coupled to the data path, the execution unit configurable to perform a group instruction that operates on a plurality of data elements in partitioned fields of a register to produce a catenated result, the execution unit further configurable to execute;
(i) an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width; and
(ii) an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the second data being permitted to cross an alignment boundary of the data width, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.
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Abstract
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.
98 Citations
26 Claims
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1. A programmable processor comprising:
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a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file coupled to the data path and containing a plurality of registers; and an execution unit coupled to the data path, the execution unit configurable to perform a group instruction that operates on a plurality of data elements in partitioned fields of a register to produce a catenated result, the execution unit further configurable to execute; (i) an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width; and (ii) an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the second data being permitted to cross an alignment boundary of the data width, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced at alignment boundaries separated by the data width. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of providing data and memory capabilities in a programmable processor, the method comprising:
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providing, in an instruction set for the processor, a group instruction that operates on a plurality of data elements in partitioned fields of at least one register to produce a catenated result; providing, in the instruction set for the processor, an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced by the data width; and providing, in the instruction set for the processor, an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced by the data width. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification