Method and apparatus for expanding a semiconductor wafer

• US 7,223,320 B2
• Filed: 06/14/2004
• Issued: 05/29/2007
• Est. Priority Date: 06/12/2003
• Status: Expired due to Fees

• Current Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Original Assignee: Symbol Technologies, Inc. (Zebra Technologies Corporation)
• Inventors: Bandy, William R., Arneson, Michael R.
• Primary Examiner(s): Osele; Mark A.
• Application Number:
  US10/866,148
• Publication Number:
  US 20040250949A1
• Time in Patent Office: 1,079 Days
• Field of Search: 156/344, 156/584, 438/464, 438/976
• US Class Current: 156/765
• CPC Class Codes: G06K 19/041 Constructional details G06K19/06 takes precedence
• CPC Class Codes: G06K 19/045 the record carrier being of the non-contact type, e.g. RFID, and being specially adapted for attachment to a disc, e.g. a CD or DVD
• CPC Class Codes: G06K 19/077 Constructional details, e.g. mounting of circuits in the carrier
• CPC Class Codes: G06K 19/07718 the record carrier being manufactured in a continuous process, e.g. using endless rolls
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28
• CPC Class Codes: G11B 23/0021 discs
• CPC Class Codes: G11B 23/0042 with provision for auxiliary features sensing such features G11B17/00, G11B19/02
• CPC Class Codes: G11B 7/26 Apparatus or processes specially adapted for the manufacture of record carriers
• CPC Class Codes: H01L 21/67132 Apparatus for placing on an insulating substrate, e.g. tape
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 21/68 for positioning, orientation or alignment
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 438/976 : Temporary protective layer
• CPC Class Codes: Y10T 156/1075 : of plural laminae from single stock and assembling to each other or to additional lamina
• CPC Class Codes: Y10T 156/1142 : Changing dimension during delaminating [e.g., crushing, expanding, warping, etc.]
• CPC Class Codes: Y10T 156/1179 : with poking during delaminating [e.g., jabbing, etc.]
• CPC Class Codes: Y10T 156/1906 : Delaminating means responsive to feed or shape at delamination
• CPC Class Codes: Y10T 156/1978 : Delaminating bending means
• CPC Class Codes: Y10T 156/1983 : Poking delaminating means
• CPC Class Codes: Y10T 29/49018 : with other electrical component
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49798 : Dividing sequentially from leading end, e.g., by cutting or breaking
• CPC Class Codes: Y10T 29/49833 : Punching, piercing or reaming part by surface of second part
• CPC Class Codes: Y10T 29/53178 : Chip component
• CPC Class Codes: Y10T 29/53187 : Multiple station assembly apparatus
• CPC Class Codes: Y10T 29/5327 : Means to fasten by deforming
• CPC Class Codes: Y10T 29/53422 : by deforming

Abstract

Methods, systems, and apparatuses are described for expanding an area of a semiconductor wafer, an enhancing die transfer capability. A wafer is attached to a support structure. The wafer is separated on the support structure into a plurality of dies. An area of the support structure is increased to increase a space between adjacent dies of the plurality of dies. Dies may be transferred from the expanded support structure.

Claims

1. A method for enhancing die transfer capability, compnsing:

(A) receiving a plurality of dies of a separated wafer on a support structure;

(B) increasing an area of the support structure to increase a space between adjacent dies of the plurality of dies;

(C) inserting a solidifiable material into the increased space between adjacent dies;

(D) causing the solidifiable material to harden into a solid grid that removably holds the plurality of dies;

(E) removing the support structure from the solid grid that removably holds the plurality of dies; and

(F) transferring at least one die of the plurality of dies from the solid grid while the solid grid remains substantially intact.

2. The method of claim 1, wherein step (F) comprises:

(1) transferring at least one die of the plurality of dies from the solid grid to a surface.

3. The method of claim 1, wherein the surface is a surface of a substrate, wherein step (1) comprises:

transferring at least one die of the plurality of dies from the solid grid to the substrate.

4. The method of claim 1, wherein step (F) comprises:

transferring the plurality of dies from the solid grid to a plurality of substrates having a spacing that corresponds to the increased space between adjacent dies of the plurality of dies.

5. The method of claim 1, wherein step (F) comprises:

transferring the plurality of dies from the solid grid to a structure having a plurality of receptacles that are spaced according to the increased space between adjacent dies of the plurality of dies.

6. The method of claim 1, wherein step (F) comprises:

(1) transferring the plurality of dies from the solid grid to a die plate having a plurality of die attach positions that are spaced according to the increased space between adjacent dies of the plurality of dies.

7. The method of claim 6, wherein step (1) comprises:

punching through holes in the die plate to transfer dies from the die plate to a subsequent surface.

8. The method of claim 1, wherein step (B) comprises:

stretching the support structure along at least one axis in a plane of the support structure.

9. The method of claim 1, further comprising:

(F) attaching a die plate to the solid grid.

10. The method of claim 1, wherein step (A) comprises:

attaching a wafer to a support structure; and

separating the wafer on the support structure into the plurality of dies.

11. The method of claim 1, wherein step (B) comprises:

stretching the support structure along a first axis.

12. The method of claim 1, wherein step (B) comprises:

stretching the support structure along a first axis and along a second axis that is orthogonal to the first axis.

13. The method of claim 1, wherein step (C) comprises:

inserting a liquid solidifiable material into the increased space between adjacent dies.

14. The method of claim 1, wherein step (C) comprises:

inserting an epoxy into the increased space between adjacent dies.