Alignment of MTJ stack to conductive lines in the absence of topography

• US 7,223,612 B2
• Filed: 07/26/2004
• Issued: 05/29/2007
• Est. Priority Date: 07/26/2004
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Sarma, Chandrasekhar
• Primary Examiner(s): Baumeister; B. William
• Assistant Examiner(s): Anya; Igwe U.
• Application Number:
  US10/899,253
• Publication Number:
  US 20060017180A1
• Time in Patent Office: 1,037 Days
• Field of Search: 438/3, 438/393, 438/401, 257/797, 257/E21.665, 257/E23.179
• US Class Current: 438/3
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a workpiece, the workplace including a first region and a second region;

forming a first insulating layer over the workplace;

forming at least one first alignment mark over the first region of the workpiece and a plurality of first conductive lines over the second region of the workpiece within the first insulating layer, the at least one first alignment mark being filled with a conductive material;

forming a second insulating layer over the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer;

forming a conductive via in the second insulating layer over the second region of the workpiece using a first lithography mask;

forming at least one second alignment mark within at least the second insulating layer over the first region of the workpiece using a second lithography mask, the second lithography mask being different from the first lithography mask, the at least one second alignment mark comprising a trench having a bottom and sidewalls;

depositing an opaque material layer over the at least one second alignment mark and the second insulating layer, the opaque material layer lining the bottom and sidewalls of the trench of the at least one second alignment mark, leaving a depression in the opaque material layer over each at least one second alignment mark;

depositing a first masking layer over the opaque material layer;

patterning the first masking layer using a lithography mask or tool, removing the first masking layer from over the at least one first alignment mark, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the first masking layer over the opaque material layer;

removing the opaque material layer from over the at least one first alignment mark using the first masking layer as a mask;

removing the first masking layer;

depositing a second masking layer over the opaque material layer and the at least one first alignment mark;

patterning the second masking layer with a pattern for the opaque material layer using the at least one first alignment mark for alignment; and

patterning the opaque material layer using the second masking layer as a mask.

2. The method according to claim 1, wherein the first masking layer or the second masking layer comprise a photoresist, or a hard mask and a photoresist.

3. The method according to claim 1, wherein forming the conductive via further comprises forming at least one third alignment mark in the second insulating layer over the first region of the workpiece, wherein the conductive via, the second insulating layer and the at least one third alignment mark comprise a substantially planar top surface.

4. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming at least one set of second alignment marks.

5. The method according to claim 4, wherein the first region and the second region of the semiconductor device comprise one of a plurality of die on the semiconductor workpiece, each die having a top edge, a bottom edge, a first side edge, and a second side edge opposite the first side edge, wherein fanning the at least one set of second alignment marks comprises fanning a first set of second alignment marks along the top edge or bottom edge of the die, and forming a second set of second alignment marks along the first side edge or the second side edge of the die.

6. The method according to claim 5, wherein forming the second alignment marks comprises forming second alignment marks having a width of about 2 μ

m or less and a length of about 60 μ

m or less.

7. The method according to claim 5, wherein the first set of second alignment marks comprises about 10 or more second alignment marks, and wherein the second set of alignment marks comprises about 10 or more second alignment marks.

8. The method according to claim 1, wherein forming the at least one second alignment mark within at least the second insulating layer comprises forming the at least one second alignment mark in at least about half the thickness of the second insulating layer.

9. The method according to claim 8, wherein forming the at least one second alignment mark within at least the second insulating layer comprises forming the at least one second alignment mark in the entire thickness of the second insulating layer.

10. The method according to claim 9, wherein forming the at least one second alignment mark further comprises forming the at least one second alignment mark within at least a portion of the first insulating layer.

11. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of about 1000 Angstroms or more.

12. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark over the first region of the workpiece yet not disposed over one of the plurality of first alignment marks in the first region of the workpiece.

13. The method according to claim 1, wherein the first region comprises a kerf or edge region of a die of the semiconductor device.

14. The method according to claim 1, wherein the semiconductor device comprises a magnetic random access memory (MRAM) device, wherein the first region comprises a kerf or edge region of a die of the MRAM device, wherein the second region comprises an array region of the MRAM device, wherein the depositing the opaque material layer comprises depositing a first magnetic stack, and wherein patterning the opaque material layer comprises forming at least one magnetic tunnel junction (MTJ).

15. The method according to claim 14, further comprising:

depositing a second magnetic stack over at least the MTJ, the second magnetic stack comprising an opaque material;

depositing a third masking layer over the second magnetic stack;

patterning the third masking layer using a lithography mask or tool, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the second masking layer over the second magnetic stack;

removing the second magnetic stack from over the at least one first alignment mark using the third masking layer as a mask;

removing the third masking layer;

depositing a fourth masking layer over the second magnetic stack and the at least one first alignment mark;

at least one first alignment mark for alignment; and

patterning the second magnetic stack using the fourth masking layer as a mask.

16. The method according to claim 14, further comprising forming a plurality of second conductive lines over each at least one MTJ.

17. The method according to claim 14, wherein the first magnetic stack comprises a first magnetic layer, a tunnel barrier disposed over the first magnetic layer, and a second magnetic layer disposed over the tunnel barrier, wherein at least the second magnetic layer comprises an opaque material.

18. A method of manufacturing a magnetic memory device, comprising:

providing a workpiece, the workplace including a plurality of die regions, each die region comprising an alignment mark region at the edges thereof, and an array region disposed within the alignment mark region;

forming a first insulating layer over the workpiece;

forming at least one first alignment mark over the alignment mark region of the workpiece and a plurality of first conductive lines over the array region of the workpiece within the first insulating layer, the at least one first alignment mark being filled wit a conductive material;

forming a second insulating layer over the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer;

forming a conductive via in the second insulating layer over the array region of the workpiece using a first lithography mask;

forming at least one second alignment mark within at least the second insulating layer over the alignment mark region of the workpiece using a second lithography mask, the second lithography mask being different from the first lithography mask, the at least one second alignment mark comprising a trench having a bottom and sidewalls, the at least one second alignment mark not being disposed over the at least one first alignment mark;

depositing a first magnetic stack over the at least one second alignment mark mid the second insulating layer, the first magnetic stack lining the bottom and sidewalls of the trench of the at least one second alignment mark, leaving a depression in the first magnetic stack over the at least one second alignment mark;

depositing a first masking layer over the first magnetic stack;

patterning the first masking layer using a lithography mask or tool, removing the first masking layer from over the at least one first alignment mark, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the first masking layer over the first magnetic stack;

removing the first magnetic stack from over the at least one first alignment mark using the first masking layer as a mask;

removing the first masking layer;

depositing a second masking layer over the first magnetic stack and the at least one first alignment mark;

patterning the second masking layer with a pattern for the first magnetic stack using the at least one first alignment mark for alignment; and

patterning the first magnetic stack using the second masking layer as a mask.

19. The method according to claim 18, wherein the first masking layer or the second masking layer comprise a photoresist, or a hard mask and a photoresist.

20. The method according to claim 18, wherein forming the conductive via further comprises forming at least one third alignment mark in the second insulating layer over the alignment mark region of the workpiece, wherein the conductive via, the second insulating layer and the at least one third alignment mark comprise a substantially planar top surface.

21. The method according to claim 18, wherein forming the at least one second alignment mark comprises forming at least one set of second alignment marks.

22. The method according to claim 21, wherein the alignment mark region comprises a top edge, a bottom edge, a first side edge, and a second side edge opposite the first side edge, wherein forming the at least one set of second alignment marks comprises forming a first set of second alignment marks along the top edge or bottom edge of the alignment mark region, and forming a second set of second alignment marks along the first side edge or the second side edge of the alignment mark region.

23. The method according to claim 22, wherein the second alignment marks comprise a width of about 2 μ

m or less and a length of about 60 μ

m or less.

24. The method according to claim 22, wherein the first set of second alignment marks comprises about 10 or more second alignment marks, and wherein the second set of alignment marks comprises about 10 or more second alignment marks.

25. The method according to claim 18, wherein forming the at least one second alignment mark within at least the second insulating layer comprises forming the at least one second alignment mark in at least about half the thickness of the second insulating layer.

26. The method according to claim 25, wherein forming the at least one second alignment mark within at least the second insulating layer comprises forming the at least one second alignment mark in the entire thickness of the second insulating layer.

27. The method according to claim 26, wherein forming the at least one second alignment mark further comprises forming the at least one second alignment mark within at least a portion of the first insulating layer.

28. The method according to claim 18, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of about 1000 Angstroms or more.

29. The method according to claim 18, wherein the magnetic memory device comprises a magnetic random access memory (MRAM) device, and wherein patterning the first magnetic stack comprises forming at least one magnetic tunnel junction (MTJ).

30. The method according to claim 29, further comprising:

depositing a second magnetic stack over at least the MTJ, the second magnetic stack comprising an opaque material;

depositing a third masking layer over the second magnetic stack;

patterning the third masking layer using a lithography mask or tool, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the second masking layer over the second magnetic stack;

removing the second magnetic stack from over the at least one first alignment mark using the third masking layer as a mask;

removing the third masking layer;

depositing a fourth masking layer over the second magnetic stack and the at least one first alignment mark;

patterning the fourth masking layer with a pattern for the second magnetic stack using the at least one first alignment mark for alignment; and

patterning the second magnetic stack using the fourth masking layer as a mask.

31. The method according to claim 29, further comprising forming a plurality of second conductive lines over each at least one MTJ.

32. The method according to claim 29, wherein the first magnetic stack comprises a first magnetic layer, a tunnel barrier disposed over the first magnetic layer, and a second magnetic layer disposed over the tunnel barrier, wherein at least the second magnetic layer comprises an opaque material.

33. A semiconductor device, comprising:

a workpiece, The workpiece including a first region and a second region;

a first insulating layer disposed over the workpiece;

at least one first alignment mark disposed over the first region of the workpiece and a plurality of first conductive lines disposed over the second region of the workpiece within the first insulating layer, the at least one first alignment mark being filled with a conductive material;

a second insulating layer disposed over the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer;

at least one second alignment mark disposed within the second insulating layer and a portion of the first insulating layer over the first region of the workpiece, the at least one second alignment mark comprising a trench having a bottom and sidewalls; and

an opaque material layer disposed over the second insulating layer, and over the at least one second alignment mark, the opaque material layer lining the bottom and sidewalls of the trench of the second alignment mark, leaving a depression in the opaque material layer over the second alignment mark.

34. The semiconductor device according to claim 33, wherein the semiconductor device comprises a magnetic random access memory (MRAM) device, wherein the first region comprises a kerf or edge region of a die of the MRAM device, wherein the second region comprises an array region of the MRAM device.