Methods for maskless lithography

• US 7,223,696 B2
• Filed: 01/27/2004
• Issued: 05/29/2007
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Trinh; Michael
• Assistant Examiner(s): Perkins; Pamela E
• Application Number:
  US10/766,557
• Publication Number:
  US 20050130351A1
• Time in Patent Office: 1,218 Days
• Field of Search: 438/690, 438/795, 438/942, 438/948, 438/949, 378/34, 378/35, 430/5
• US Class Current: 438/690
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2203/075 the electronic processing unit being integrated into an element of the micromechanical structure
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 438/949 : Energy beam treating radiation resist on semiconductor

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of maskless lithographic pattern generation using an array of exposure cells, wherein a plurality of the exposure cells expose separate areas of a surface to be exposed, and wherein the plurality of the exposure cells are capable of independent simultaneous operation;

providing at least one dielectric layer; and

providing a plurality of interconnect conductors formed at least one of through and within the at least one dielectric layer.

2. The method of claim 1, wherein a substantial portion of the separate areas are exposed simultaneously.

3. The method of claim 1, further comprising moving through a sequence of horizontal and vertical motions at least one of the array of exposure cells and the surface to be exposed.

4. The method of claim 1, further comprising aligning by electro-magnetic coupling the array of exposure cells and the surface to be exposed.

5. The method of claim 1, wherein each exposure cell is selected from the group consisting of a radiation source cell or a shuttered cell.

6. The method of claim 1, wherein the shutter of a shuttered cell is used to vary operation of the exposure cell.

7. The method of claim 1, wherein radiation from a radiation source cell is selected from the group consisting of electrons, protons, X-ray, UV or optical.

8. The method of claim 1, wherein the array of exposure cells includes at least one million cells.

9. The method of claim 1, wherein the at least one dielectric layer is a stress-controlled dielectric layer.

10. The method of claim 9, wherein the stress of the at least one stress-controlled dielectric layer is less than about 8×

10₈ dynes/cm₂.

11. The method of claim 10, wherein the stress is tensile.

12. The method of claim 9, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

13. The method of claim 12, wherein the stress is tensile.

14. The method of claim 9, wherein the at least one stress-controlled dielectric layer is selected from the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

15. The method of claim 9, wherein the at least one stress-controlled dielectric layer is elastic.

16. The method of claim 9, wherein the at least one stress-controlled dielectric layer is substantially flexible.

17. The method of claim 9, wherein the at least one stress-controlled dielectric layer is capable of forming at least one of a flexible membrane and a free standing membrane.

18. The method of claim 9, wherein the at least one stress-controlled dielectric layer is formed by multiple RF energy sources.

19. The method of claim 9, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.

20. The method of claim 1, further comprising providing at least one thinned flexible substrate that has integrated circuitry with active devices formed thereon.

21. A method of maskless lithographic pattern generation, the method comprising:

providing an array of exposure cells formed on a substrate, wherein a plurality of the exposure cells expose separate areas of a surface to be exposed; and

providing a low stress and elastic dielectric layer on the substrate.

22. The method of claim 21, wherein a substantial portion of the separate areas are exposed simultaneously.

23. The method of claim 21, further comprising moving through a sequence of horizontal and vertical motions at least one of the array of exposure cells and the surface to be exposed.

24. The method of claim 21, further comprising aligning by electro-magnetic coupling the array of exposure cells and the surface to be exposed.

25. The method of claim 21, wherein each exposure cell is selected from the group consisting of a radiation source cell and a shuttered cell.

26. The method of claim 21, wherein the shutter of a shuttered cell is used to vary operation of the exposure cell.

27. The method of claim 21, wherein radiation from a radiation source cell is selected from the group consisting of electrons, protons, X-ray, UV or optical.

28. The method of claim 21, wherein at least one of the following conditions is true:

(1) the stress of the low stress and elastic dielectric layer is less than about 8×

10₈ dynes/cm₂;

(2) the low stress and elastic dielectric is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane; and

(3) the low stress and elastic dielectric layer is selected from the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

29. The method of claim 28, wherein the stress is tensile.

30. The method of claim 21, wherein the array of exposure cells includes at least one million cells.

31. The method of claim 21, further comprising providing at least one stress-controlled dielectric layer.

32. The method of claim 31, wherein the at least one stress-controlled dielectric layer is selected from the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

33. The method of claim 31, wherein the at least one stress-controlled dielectric layer is elastic.

34. The method of claim 31, wherein the at least one stress-controlled dielectric layer is substantially flexible.

35. The method of claim 31, wherein the at least one stress-controlled dielectric layer is capable of forming at least one of a flexible membrane and a free standing membrane.

36. The method of claim 31, wherein the at least one stress-controlled dielectric layer is formed by multiple RF energy sources.

37. The method of claim 31, wherein the at least one stress-controlled dielectric layer is formed at a temperature of about 400°

C.

38. The method of claim 21, wherein the stress of the at least one stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the at least one stress-controlled dielectric layer.

39. The method of claim 38, wherein the stress is tensile.

40. The method of claim 21, wherein the substrate has integrated circuitry with active devices formed thereon.

41. The method of claim 21, wherein the low stress and elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane, and a free standing membrane.

42. The method of claim 21, wherein the low stress and elastic dielectric layer is selected from the group consisting of an oxide of silicon, a nitride of silicon, silicon dioxide, and silicon nitride.

43. A method of maskless lithographic pattern generation using an array of exposure cells wherein the exposure cells expose separate areas of a surface to be exposed, further comprising:

providing at least one stress-controlled dielectric layer; and

providing a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.

44. A method of maskless lithographic pattern generation, the method comprising:

providing an array of exposure cells on a substrate, wherein the exposure cells expose separate areas of a surface to be exposed;

providing a stress-controlled dielectric layer on the substrate;

providing at least one stress-controlled dielectric layer; and

providing a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.