Methods for maskless lithography
First Claim
1. A method of maskless lithographic pattern generation using an array of exposure cells, wherein a plurality of the exposure cells expose separate areas of a surface to be exposed, and wherein the plurality of the exposure cells are capable of independent simultaneous operation;
- providing at least one dielectric layer; and
providing a plurality of interconnect conductors formed at least one of through and within the at least one dielectric layer.
1 Assignment
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Accused Products
Abstract
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
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Citations
44 Claims
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1. A method of maskless lithographic pattern generation using an array of exposure cells, wherein a plurality of the exposure cells expose separate areas of a surface to be exposed, and wherein the plurality of the exposure cells are capable of independent simultaneous operation;
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providing at least one dielectric layer; and providing a plurality of interconnect conductors formed at least one of through and within the at least one dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of maskless lithographic pattern generation, the method comprising:
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providing an array of exposure cells formed on a substrate, wherein a plurality of the exposure cells expose separate areas of a surface to be exposed; and providing a low stress and elastic dielectric layer on the substrate. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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43. A method of maskless lithographic pattern generation using an array of exposure cells wherein the exposure cells expose separate areas of a surface to be exposed, further comprising:
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providing at least one stress-controlled dielectric layer; and providing a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.
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44. A method of maskless lithographic pattern generation, the method comprising:
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providing an array of exposure cells on a substrate, wherein the exposure cells expose separate areas of a surface to be exposed; providing a stress-controlled dielectric layer on the substrate; providing at least one stress-controlled dielectric layer; and providing a plurality of interconnect conductors formed within the at least one stress-controlled dielectric layer.
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Specification