Strained Si on multiple materials for bulk or SOI substrates

• US 7,223,994 B2
• Filed: 06/03/2004
• Issued: 05/29/2007
• Est. Priority Date: 06/03/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Zhu, Huilong, Dokumaci, Omer H., Gluschenkov, Oleg G.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US10/859,736
• Publication Number:
  US 20050269561A1
• Time in Patent Office: 1,090 Days
• Field of Search: 257 18- 20, 257/103, 257190-194, 257350-354
• US Class Current: 257/18
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

Claims

1. A semiconducting material comprising:

a substrate;

a first layered stack atop said substrate, said first layered stack comprising a first Si-containing portion of said substrate, a compressive layer having a lower surface that is in direct contact with an upper surface of said first Si-containing portion of said substrate, and a first semiconducting layer atop said compressive layer; and

a second layered stack atop said substrate, said second layered stack comprising a second Si-containing portion of said substrate, a tensile layer having a lower surface that is in direct contact with an upper surface of said second Si-containing portion of said substrate, and a second semiconducting layer atop said tensile layer.

2. The semiconducting substrate of claim 1 wherein said substrate is a silicon-on-insulating substrate or a bulk-silicon substrate.

3. The semiconducting substrate of claim 1 wherein said compressive layer comprises SiGe having Ge present in a concentration ranging from about 5% to about 30% by atomic weight percent.

4. The semiconducting substrate of claim 1 wherein said tensile layer comprises silicon doped with carbon, said carbon is present in a concentration ranging from about 1% to 6% by atomic weight percent.

5. The semiconducting substrate of claim 1 wherein said compressive layer elastically transfers tensile stresses to said first semiconducting layer.

6. The semiconducting substrate of claim 1 wherein said tensile layer elastically transfers compressive stresses to said second semiconducting layer.

7. The semiconducting substrate of claim 1 wherein said compressive layer and said tensile layer have a thickness ranging from about 10 nm to about 100 nm.

8. The semiconducting substrate of claim 1 wherein at least one nFET device is formed atop said first layered stack.

9. The semiconducting device of claim 1 wherein at least one pFET device is formed atop said second layered stack.

10. The semiconductor substrate of claim 1 wherein said first layered stack and said second layered stack are separated by an isolation region.