Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors

• US 7,223,996 B2
• Filed: 05/31/2005
• Issued: 05/29/2007
• Est. Priority Date: 05/29/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Pham; Thanh V.
• Application Number:
  US11/139,494
• Publication Number:
  US 20050214990A1
• Time in Patent Office: 728 Days
• Field of Search: 257/57, 257/66, 257/347, 257/E27.131, 257/E29.151, 438/149, 438/157, 438163-164, 438/FOR.184
• US Class Current: 257/57
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Claims

1. A semiconductor device characterized in that:

the semiconductor device comprises at least two thin film transistors connected in series in a pixel portion, the two thin film transistors comprising;

a silicon nitride film formed over a substrate;

a silicon oxide film formed over the silicon nitride film;

first and second semiconductor islands formed over the silicon oxide film;

a gate insulating film formed over the first and second semiconductor islands;

first and second gate electrodes formed adjacent to the first and second semiconductor islands, respectively, with the gate insulating film interposed therebetween;

wherein the gate insulating film is extended between the first and second semiconductor islands,

wherein the two thin film transistors are electrically connected to a pixel electrode.

2. A semiconductor device according to claim 1, wherein the thin film transistors are p-channel thin film transistors.

3. A semiconductor device according to claim 1, wherein the silicon nitride film has a thickness in a range of 5-200 nm, and the silicon oxide film with a thickness in a range of 20-1000 nm.

4. A semiconductor device according to claim 1, wherein the channel region comprises an amorphous silicon layer and a crystalline silicon layer on the amorphous silicon layer.

5. A semiconductor device characterized in that:

the semiconductor device comprises at least two p-channel thin film transistors connected in series in a pixel portion, the p-channel thin film transistors comprising;

a silicon nitride film formed over a substrate;

a silicon oxide film formed over the silicon nitride film;

first and second semiconductor islands formed over the silicon oxide film;

a gate insulating film formed over the first and second semiconductor islands;

first and second gate electrodes formed adjacent to the first and second semiconductor islands, respectively, with the gate insulating film interposed therebetween;

wherein the gate insulating film is extended between the first and second semiconductor islands,

wherein the two p-channel thin film transistors are electrically connected to a pixel electrode.

6. A semiconductor device according to claim 5, wherein the silicon nitride film has a thickness in a range of 5-200 nm, and the silicon oxide film with a thickness in a range of 20-1000 nm.

7. A semiconductor device according to claim 5, wherein the channel region comprises an amorphous silicon layer and a crystalline silicon layer on the amorphous silicon layer.

8. A semiconductor device characterized in that:

the semiconductor device comprises at least two p-channel thin film transistors connected in series in a pixel portion, the p-channel thin film transistors comprising;

a silicon nitride film formed over a substrate;

a silicon oxide film formed over the silicon nitride film;

first and second semiconductor islands formed over the silicon oxide film;

a gate insulating film formed over the first and second semiconductor islands;

first and second gate electrodes formed adjacent to the first and second semiconductor islands, respectively, with the gate insulating film interposed therebetween;

an interlayer insulating film over the first and second gate electrodes and the gate insulating film,

wherein the gate insulating film is extended between the first and second semiconductor islands,

wherein the interlayer insulating film is formed over the gate insulating film which is extended between the first and second semiconductor islands, and

wherein the two p-channel thin film transistors are electrically connected to a pixel electrode.

9. A semiconductor device according to claim 8, wherein the silicon nitride film has a thickness in a range of 5-200 nm, and the silicon oxide film with a thickness in a range of 20-1000 nm.

10. A semiconductor device according to claim 8, wherein the channel region comprises an amorphous silicon layer and a crystalline silicon layer on the amorphous silicon layer.

11. A semiconductor device according to claim 8, wherein the interlayer insulating film includes silicon oxide or boro-phosphosilicate glass.

12. A semiconductor device characterized in that:

the semiconductor device comprises at least two p-channel thin film transistors connected in series in a pixel portion, the p-channel thin film transistors comprising;

a silicon nitride film formed over a substrate;

a silicon oxide film formed over the silicon nitride film;

first and second semiconductor islands formed over the silicon oxide film;

a gate insulating film formed over the first and second semiconductor islands;

first and second gate electrodes formed adjacent to the first and second semiconductor islands, respectively, with the gate insulating film interposed therebetween;

wherein the gate insulating film is extended between the first and second semiconductor islands,

wherein the two p-channel thin film transistors are electrically connected to a pixel electrode, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

13. A semiconductor device according to claim 12, wherein the silicon nitride film has a thickness in a range of 5-200 nm, and the silicon oxide film with a thickness in a range of 20-1000 nm.

14. A semiconductor device according to claim 12, wherein the channel region comprises an amorphous silicon layer and a crystalline silicon layer on the amorphous silicon layer.

15. A semiconductor device characterized in that:

the semiconductor device comprises at least two p-channel thin film transistors connected in series in a pixel portion, the p-channel thin film transistors comprising;

a silicon nitride film formed over a substrate;

a silicon oxide film formed over the silicon nitride film;

first and second semiconductor islands formed over the silicon oxide film;

a gate insulating film formed over the first and second semiconductor islands;

first and second gate electrodes formed adjacent to the first and second semiconductor islands, respectively, with the gate insulating film interposed therebetween;

an interlayer insulating film over the first and second gate electrodes and the gate insulating film,

wherein the gate insulating film is extended between the first and second semiconductor islands,

wherein the interlayer insulating film is formed over the gate insulating film which is extended between the first and second semiconductor islands,

wherein the two p-channel thin film transistors are electrically connected to a pixel electrode, and

wherein a pixel electrode is connected to a data line without any n-channel thin film transistor connected therebetween.

16. A semiconductor device according to claim 15, wherein the silicon nitride film has a thickness in a range of 5-200 nm, and the silicon oxide film with a thickness in a range of 20-1000 nm.

17. A semiconductor device according to claim 15, wherein the channel region comprises an amorphous silicon layer and a crystalline silicon layer on the amorphous silicon layer.

18. A semiconductor device according to claim 15, wherein the interlayer insulating film includes silicon oxide or boro-phosphosilicate glass.