Design and fabrication of 6.1-Å family semiconductor devices using semi-insulating A1Sb substrate

• US 7,224,041 B1
• Filed: 05/28/2004
• Issued: 05/29/2007
• Est. Priority Date: 09/30/2003
• Status: Expired due to Fees

• Current Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Wu, Kuang Jen J., Coombs, Arthur W. III, Sherohman, John W., Yee, Jick Hong
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US10/856,175
• Publication Number:
  US 20070131161A1
• Time in Patent Office: 1,096 Days
• Field of Search: 257/22, 257/183, 257/190, 257/201
• US Class Current: 257/613
• CPC Class Codes: H01L 21/02398 Antimonides
• CPC Class Codes: H01L 21/02466 Antimonides
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/02551 Group 12/16 materials
• CPC Class Codes: H01L 21/0256 Selenides
• CPC Class Codes: H01L 21/02562 Tellurides
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 31/0328 including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/109 the potential barrier being of the PN heterojunction type

Abstract

For the first time, an aluminum antimonide (AlSb) single crystal substrate is utilized to lattice-match to overlying semiconductor layers. The AlSb substrate establishes a new design and fabrication approach to construct high-speed, low-power electronic devices while establishing inter-device isolation. Such lattice matching between the substrate and overlying semiconductor layers minimizes the formation of defects, such as threaded dislocations, which can decrease the production yield and operational life-time of 6.1-Å family heterostructure devices.

Claims

1. A method of forming a semiconductor device, comprising:

providing a bulk single crystal semi-insulating AlSb substrate having a resistivity of greater than about 10⁷ Ω

·

cm; and

growing one or more semiconductor layers substantially lattice matched to said bulk single crystal semi-insulating AlSb substrate.

2. The method of claim 1, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about −

4.5 μ

amps and about +4 μ

amps when subjected to respective voltages between about −

10 volts and about +10 volts.

3. The method of claim 1, wherein said one or more semiconductor layers comprises a compound from the 6.1-Å

family III-V semiconductor family.

4. The method of claim 1, wherein said one or more semiconductor layers comprises a compound from the 6.1-Å

family II-VI semiconductor family.

5. The method of claim 1, wherein said one or more semiconductor layers further comprise alternating layers of doped and undoped semiconductor materials.

6. A method of forming a semiconductor device, comprising:

providing a bulk single crystal semi-insulating AlSb substrate having a resistivity of greater than about 10⁷ Ω

·

cm; and

growing a semiconductor heterostructure substantially lattice matched to said bulk single crystal semi-insulating AlSb substrate, wherein said semiconductor device further comprises one or more buffer layers intermediate said bulk single crystal semi-insulating AlSb substrate and said semiconductor heterostructure.

7. The method of claim 6, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about −

4.5 μ

amps and about +4 μ

amps when subjected to respective voltages between about −

10 volts and about +10 volts.

8. The method of claim 6, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

III-V family.

9. The method of claim 6, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

II-VI family.

10. The method of claim 6, wherein said one or more buffer layers are arranged so as to provide crystal lattice matching, electrical isolation and/or surface smoothing.

11. A semiconductor device, comprising:

a bulk single crystal semi-insulating AlSb substrate having a resistivity of greater than about 10⁷ Ω

·

cm; and

one or more semiconductor layers grown on said bulk single crystal semi-insulating AlSb substrate, wherein said one or more semiconductor layers are substantially lattice matched to said bulk single crystal semi-insulating AlSb substrate.

12. The semiconductor device of claim 11, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about −

4.5 μ

amps and about +4 μ

amps when subjected to respective voltages between about −

10 volts and about +10 volts.

13. The semiconductor device of claim 11, wherein said one or more semiconductor layers further comprise one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

III-V family.

14. The semiconductor device of claim 11, wherein said one or more semiconductor layers further comprise one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

II-VI family.

15. The semiconductor device of claim 11, wherein said semiconductor layers are formed by molecular beam epitaxy.

16. The semiconductor device of claim 11, wherein said one or more semiconductor layers further comprise alternating layers of doped and undoped semiconductor materials.

17. A semiconductor device, comprising:

a bulk single crystal semi-insulating AlSb substrate having a resistivity of greater than about 10⁷ Ω

·

cm; and

a semiconductor heterostructure grown on said bulk single crystal semi-insulating AlSb base substrate, wherein said heterostructure comprises substantial lattice matching to said bulk single crystal semi-insulating AlS substrate and wherein said heterostructure further comprises one or more buffer layers intermediate said AlSb substrate and said heterostructure.

18. The semiconductor device of claim 17, wherein said AlSb substrate is arranged to have a uniform resistivity capable of a providing a current between about −

4.5 μ

amps and about +4 μ

amps when subjected to respective voltages between about −

10 volts and about +10 volts.

19. The semiconductor device of claim 17, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

III-V family.

20. The semiconductor device of claim 17, wherein said semiconductor heterostructure further comprises one or more binary, ternary, or quaternary, semiconductor layers comprising the 6.1-Å

II-VI family.

21. The semiconductor device of claim 17, wherein said buffer layer is arranged so as to provide crystal lattice matching, electrical isolation and/or surface smoothing.

22. The semiconductor device of claim 17, wherein said semiconductor heterostructure is formed by molecular beam epitaxy.

23. The semiconductor device of claim 17, wherein said semiconductor heterostructure further comprises alternating layers of doped and undoped semiconductor materials.