Semiconductor device having conductive interconnections and porous and nonporous insulating portions

• US 7,224,064 B2
• Filed: 01/24/2005
• Issued: 05/29/2007
• Est. Priority Date: 02/02/2001
• Status: Expired due to Fees

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yoshie, Toru
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US11/042,033
• Publication Number:
  US 20050133923A1
• Time in Patent Office: 855 Days
• Field of Search: 257758-760, 257/762, 257774-776, 257/E23.144, 257/E23.145, 257/E23.167, 257/E23.262, 257/E21.581, 257/E23.16, 257/E23.577, 257/E21.579, 257/552, 257/700, 257/701, 257/741, 257/750, 257/618
• US Class Current: 257/758
• CPC Class Codes: B24B 37/04 designed for working plane surfaces
• CPC Class Codes: B24B 57/02 for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 : Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1047 : the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and manufacturing method, wherein the semiconductor device has a semiconductor substrate on which a plurality of elements constituting a logic type device have been formed; a first interlayer insulating film on the semiconductor substrate; a plurality of groove patterns provided in the first interlayer insulating film; lower interconnections formed by embedding electroconductive films, which are composed of an electroconductive material such as copper, in the groove patterns; and first porous portions that are selectively provided in the portions of the first interlayer insulating film having the lower interconnections formed therein, the portions being in contact with the lower interconnections. A semiconductor device having an interlayer insulating film that exhibits satisfactory mechanical strengths, thermal conductivity and low dielectric constant is thus provided.

Claims

1. A semiconductor device comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous insulating portion having a first groove, a second porous insulating portion having a second groove and a nonporous insulating portion located between the first and second porous insulating portions; and

a plurality of interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove,

wherein the interconnections comprise third, fourth, fifth, and sixth conductive patterns provided spaced away from each other, and

a distance between the third conductive pattern and the fourth conductive pattern is shorter than a distance between the fifth conductive pattern and the sixth conductive pattern.

2. A semiconductor device according to claim 1, wherein the distance between the third conductive pattern and the fourth conductive pattern is about 800 nm or less.

3. A semiconductor device comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous insulating portion having a first groove, a second porous insulating portion having a second groove and a nonporous insulating portion located between the first and second porous insulating portions; and

a plurality of interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove,

wherein the porous insulating portions are composed of an insulating film that has been perforated at about 70% of an entire area thereof.

4. A semiconductor device comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous insulating portion having a first groove, a second porous insulating portion having a second groove and a nonporous insulating portion located between the first and second porous insulating portions; and

a plurality of interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove,

wherein the insulating film includes an additive substance added thereto.

5. A semiconductor device comprising:

a substrate;

a first insulating film formed on the substrate, the first insulating film including a first porous insulating portion having a first groove, a second porous insulating portion having a second groove and a first nonporous insulating portion located between the first and second porous insulating portions;

a plurality of lower interconnections including a first conductive pattern disposed in the first groove and a second conductive pattern disposed in the second groove;

a second insulating film formed on the first insulating film and the lower interconnections;

a plurality of openings formed in the second insulating film on the lower interconnections; and

a plurality of upper interconnections that are embedded in the openings and electrically connected with the lower interconnections,

wherein the second insulating film in which the upper interconnections are formed comprises a plurality of third porous insulating portions provided in contact with the upper interconnections, and a plurality of second nonporous insulating portions provided in contact with the third porous insulating portions.

6. A semiconductor device according to claim 5, wherein the third porous insulating portions are composed of the second insulating film comprising a plurality of voids.

7. A semiconductor device according to claim 5, wherein the openings comprise grooves, and connecting holes extending from bottom surfaces of the grooves to the lower interconnections,

the upper interconnections comprise upper layer conductive patterns embedded in the grooves, and connecting plugs electrically connecting the upper layer conductive patterns and the lower interconnections, and

the third porous insulating portions are provided in contact with side surfaces of the upper interconnections, the second nonporous insulating portions are provided in contact with the third porous insulating portions, and fourth nonporous insulating portions are in contact with bottom surfaces of the upper layer conductive patterns and are provided in the second insulating film.

8. A semiconductor device according to claim 5, wherein the conductive patterns are composed of an electroconductive material, including Cu.

9. A semiconductor device according to claim 5, wherein the porous insulating portions are composed respectively of the first and second insulating films that have been perforated at about 70% of an entire area thereof.

10. A semiconductor device according to claim 5, wherein the first and second insulating films have an additive substance added thereto.