Plurality of semiconductor die in an assembly

• US 7,224,070 B2
• Filed: 05/24/2004
• Issued: 05/29/2007
• Est. Priority Date: 09/21/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yang, Jicheng
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/852,315
• Publication Number:
  US 20040212082A1
• Time in Patent Office: 1,100 Days
• Field of Search: 257/777, 257/718, 257/723, 257/690, 361/396, 361/735, 438/455, 438/106, 438/107, 438/109, 438/124, 438/127, 438/405, 438/406, 298/41
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/26145 Flow barriers
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/27013 for holding or confining the layer connector, e.g. solder flow barrier
• CPC Class Codes: H01L 2224/29012 in top view
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83051 Forming additional members, e.g. dam structures
• CPC Class Codes: H01L 2224/83139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.

Claims

1. A plurality of semiconductor die for an assembly comprising:

a first semiconductor die of a plurality of semiconductor die in a wafer, the first semiconductor die having an upper surface, the upper surface comprising a plurality of electrical contacts and at least one region for mounting a second semiconductor die;

at least one adhesive flow control dam formed on the first semiconductor die when a plurality of semiconductor die are in a wafer form prior to the singulation of the plurality of semiconductor die from the wafer for preventing flow of an adhesive applied in the at least one region of the first semiconductor die onto the plurality of electrical contacts during the mounting of a second semiconductor die, the at least one adhesive flow control dam positioned between the at least one region for mounting a second semiconductor die and each electrical contact of the plurality of electrical contacts; and

a second semiconductor die, the second semiconductor die adhesively mounted onto the at least one region for the mounting a second semiconductor die of the first semiconductor die.

2. The plurality of semiconductor die of claim 1, further comprising an encapsulant surrounding at least a portion of surface area of the first semiconductor die and the second semiconductor die.

3. The plurality of semiconductor die of claim 1, further comprising a carrier substrate, the first semiconductor die being disposed on the carrier substrate.

4. The plurality of semiconductor die of claim 1, further comprising a mounting adhesive disposed on at least a portion of a region of the upper surface of the first semiconductor die, at least a portion of the mounting adhesive disposed between the at least one adhesive flow control dam and the second semiconductor die.

5. The plurality of semiconductor die of claim 4, wherein the mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.

6. The plurality of semiconductor die of claim 5, wherein the mounting adhesive comprises an Ag-filled polymer.

7. The plurality of semiconductor die of claim 4, wherein the mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of the first semiconductor die, a coefficient of thermal expansion of the second semiconductor die, and an average of the coefficients of thermal expansion of the first semiconductor die and the second semiconductor die.

8. The plurality of semiconductor die of claim 1, wherein the at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.

9. The plurality of semiconductor die of claim 8, wherein an adhesive used to mount the second semiconductor die includes an electrically insulating adhesive.

10. The plurality of semiconductor die of claim 1, wherein the at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.

11. The plurality of semiconductor die of claim 1, wherein the at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount the second semiconductor die.

12. The plurality of semiconductor die of claim 1, wherein the first semiconductor die is larger than the second semiconductor die.

13. The plurality of semiconductor die of claim 1, wherein the first semiconductor die is substantially the same size as the second semiconductor die.

14. The plurality of semiconductor die of claim 1, wherein the first semiconductor die comprises an integrated circuit semiconductor die.

15. The plurality of semiconductor die of claim 1, wherein the second semiconductor die comprises an integrated circuit semiconductor die.

16. The plurality of semiconductor die of claim 14, wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

17. The plurality of semiconductor die of claim 15, wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

18. The plurality of semiconductor die of claim 1, wherein the first semiconductor die comprises an interposer.

19. The plurality of semiconductor die of claim 1, wherein the second semiconductor die is mounted in an offset fashion relative to the first semiconductor die.

20. The plurality of semiconductor die of claim 1, wherein at least a portion of the second semiconductor die is in contact with the at least one adhesive flow control dam.

21. The plurality of semiconductor die of claim 20, wherein the at least one adhesive flow control dam is configured to deform upon the contact with the second semiconductor die.

22. The plurality of semiconductor die of claim 1, wherein the at least one adhesive flow control dam extends substantially across an entire width of the first semiconductor die.

23. The plurality of semiconductor die of claim 1, further comprising at least one wire bond extending from at least one electrical contact of the plurality of electrical contacts.

24. The plurality of semiconductor die of claim 23, wherein the at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of the second semiconductor die or an extension thereof during wire bonding of at least one electrical contact of the plurality of electrical contacts.

25. A stacked semiconductor die assembly comprising:

a first semiconductor die of a plurality of semiconductor die in a wafer, the first semiconductor die having an upper surface including a plurality of electrical contacts, at least one region for mounting a second semiconductor die, and at least one adhesive flow control dam formed on the first semiconductor die when a plurality of semiconductor die are in a wafer form prior to the singulation of the plurality of semiconductor die from the wafer for preventing flow of an adhesive from the at least one region onto the plurality of electrical contacts during the mounting of a second semiconductor die on the first semiconductor die, the at least one adhesive flow control dam positioned between the at least one region for mounting a second semiconductor die and each electrical contact of the plurality of electrical contacts; and

a second semiconductor die, the second semiconductor die adhesively mounted onto the at least one region for the mounting a second semiconductor die of the first semiconductor die.

26. The stacked semiconductor die assembly of claim 25, further comprising an encapsulant surrounding at least a portion of a surface area of the first semiconductor die and the second semiconductor die.

27. The stacked semiconductor die assembly of claim 25, further comprising a carrier substrate, the first semiconductor die being disposed on the carrier substrate.

28. The stacked semiconductor die assembly of claim 25, further comprising a mounting adhesive disposed on at least a portion of a region of the upper surface of the first semiconductor die, at least a portion of the mounting adhesive disposed between the at least one adhesive flow control dam and the second semiconductor die.

29. The stacked semiconductor die assembly of claim 28, wherein the mounting adhesive is configured to be thermally conductive having an exposed surface area being heat dissipative.

30. The stacked semiconductor die assembly of claim 29, wherein the mounting adhesive comprises an Ag-filled polymer.

31. The stacked semiconductor die assembly of claim 28, wherein the mounting adhesive is configured to have a coefficient of thermal expansion selected from a group consisting of a coefficient of thermal expansion of the first semiconductor die, a coefficient of thermal expansion of the second semiconductor die, and an average of the coefficients of thermal expansion of the first semiconductor die and the second semiconductor die.

32. The stacked semiconductor die assembly of claim 25, wherein the at least one adhesive flow control dam comprises at least one decoupling capacitor coupon.

33. The stacked semiconductor die assembly of claim 32, wherein an adhesive used to mount the second semiconductor die includes an electrically insulating adhesive.

34. The stacked semiconductor die assembly of claim 25, wherein the at least one adhesive flow control dam comprises a material selected from a group consisting of polyimides, polyamides, and epoxies.

35. The stacked semiconductor die assembly of claim 25, wherein the at least one adhesive flow control dam includes a flow control dam more viscous than an adhesive used to adhesively mount the second semiconductor die.

36. The stacked semiconductor die assembly of claim 25, wherein the first semiconductor die is larger than the second semiconductor die.

37. The stacked semiconductor die assembly of claim 25, wherein the first semiconductor die is substantially the same size as the second semiconductor die.

38. The stacked semiconductor die assembly of claim 25, wherein the first semiconductor die comprises an integrated circuit semiconductor die.

39. The stacked semiconductor die assembly of claim 25, wherein the second semiconductor die comprises an integrated circuit semiconductor die.

40. The stacked semiconductor die assembly of claim 38, wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

41. The stacked semiconductor die assembly of claim 39, wherein the integrated circuit semiconductor die is selected from a group consisting of microprocessors, DRAM, SRAM, FLASH, ADC, FGPA, an active pixel sensor, and an operation amplifier.

42. The stacked semiconductor die assembly of claim 25, wherein the first semiconductor die comprises an interposer.

43. The stacked semiconductor die assembly of claim 25, wherein the second semiconductor die is mounted in an offset fashion relative to the first semiconductor die.

44. The stacked semiconductor die assembly of claim 25, wherein at least a portion of the second semiconductor die is in contact with the at least one adhesive flow control dam.

45. The stacked semiconductor die assembly of claim 44, wherein the at least one adhesive flow control dam is configured to deform upon the contact with the second semiconductor die.

46. The stacked semiconductor die assembly of claim 25, wherein the at least one adhesive flow control dam extends substantially across an entire width of the first semiconductor die.

47. The stacked semiconductor die assembly of claim 25, further comprising at least one wire bond extending from at least one electrical contact of the plurality of electrical contacts.

48. The stacked semiconductor die assembly of claim 47, wherein the at least one adhesive flow control dam is further configured to prevent solder flow onto at least a portion of the second semiconductor die or an extension thereof during wire bonding of at least one electrical contact of the plurality of electrical contacts.