Clock distribution in a configurable IC

• US 7,224,181 B1
• Filed: 03/15/2005
• Issued: 05/29/2007
• Est. Priority Date: 11/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/082,201
• Time in Patent Office: 805 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/38
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

Some embodiments of the invention provide a reconfigurable IC that has several reconfigurable circuits. Each reconfigurable circuit for reconfigurably performing a set of operations and for reconfiguring at a first frequency. The reconfigurable IC also has at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency. The reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

Claims

1. A reconfigurable IC comprising:

a) a plurality of reconfigurable circuits each for configurably performing a set of operations and for reconfiguring at a first frequency;

b) at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency;

c) wherein said reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

2. The reconfigurable IC of claim 1, wherein the first frequency is faster than the second and third frequencies.

3. The reconfigurable IC of claim 2, wherein the second frequency is faster than the third frequency.

4. The reconfigurable IC of claim 1, wherein the set of reconfiguration signals includes a plurality of signals that have different phases.

5. The reconfigurable IC of claim 1, wherein the set of reconfiguration signals is a set that includes at least two signals that are never active at the same time.

6. The reconfigurable IC of claim 1 further comprising a plurality of reconfiguration signal generators for a plurality of sets of reconfigurable circuits.

7. The reconfigurable IC of claim 6, wherein sets of reconfigurable circuits form a tile layout that defines a unit of replica in the reconfigurable IC, wherein the reconfigurable IC includes at least one reconfiguration signal generator for each tile layout.

8. The reconfigurable IC of claim 7 further comprising:

a) a plurality of global clock generators for distributing a plurality of global clock signals;

b) interconnects in the tile layouts for receiving a plurality of global clock signals and selectively directing one of the global clock signals to the reconfiguration signal generator in the tile layouts.

9. The reconfigurable IC of claim 8, wherein the tile layout includes first and second reconfiguration signal generators, said reconfigurable circuits includes reconfigurable logic circuits and reconfigurable interconnect circuits, wherein the logic circuits operate based on reconfiguration signals generates by the first reconfiguration signal generator, while the interconnect circuits operation based on reconfiguration signals generated by the second reconfiguration signal generator.

10. An electronic device comprising:

a) A reconfigurable IC comprising;

a plurality of reconfigurable circuits each for configurably performing a set of operations and for reconfiguring at a first frequency;

at least one reconfiguration signal generator for receiving a clock signal at a second frequency and producing a set of reconfiguration signals with a third frequency;

wherein said reconfiguration signals are supplied to the reconfigurable circuits to direct the reconfiguration of the reconfigurable circuits at the first frequency.

11. The reconfigurable IC of claim 10, wherein the first frequency is faster than the second and third frequencies.

12. The reconfigurable IC of claim 11, wherein the second frequency is faster than the third frequency.

13. The reconfigurable IC of claim 10, wherein the set of reconfiguration signals includes a plurality of signals that have different phases.

14. The reconfigurable IC of claim 10, wherein the set of reconfiguration signals is a set that includes at least two signals that are never active at the same time.

15. The reconfigurable IC of claim 10 further comprising a plurality of reconfiguration signal generators for a plurality of sets of reconfigurable circuits.

16. The reconfigurable IC of claim 15, wherein sets of reconfigurable circuits form a tile layout that defines a unit of replica in the reconfigurable IC, wherein the reconfigurable IC includes at least one reconfiguration signal generator for each tile layout.

17. The reconfigurable IC of claim 16 further comprising:

a) a plurality of global clock generators for distributing a plurality of global clock signals;

b) interconnects in the tile layouts for receiving a plurality of global clock signals and selectively directing one of the global clock signals to the reconfiguration signal generator in the tile layouts.

18. The reconfigurable IC of claim 17, wherein the tile layout includes first and second reconfiguration signal generators, said reconfigurable circuits includes reconfigurable logic circuits and reconfigurable interconnect circuits, wherein the logic circuits operate based on reconfiguration signals generates by the first reconfiguration signal generator, while the interconnect circuits operation based on reconfiguration signals generated by the second reconfiguration signal generator.