Semiconductor circuit device

• US 7,224,186 B2
• Filed: 02/17/2005
• Issued: 05/29/2007
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Tsukada, Shuichi
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/060,391
• Publication Number:
  US 20050184759A1
• Time in Patent Office: 831 Days
• Field of Search: 326/63, 326/68, 326 80- 83, 326/86
• US Class Current: 326/83
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

The present invention relates to a semiconductor circuit device including a logic circuit and a signal line driving circuit. The logic circuit is operated at high supply voltage and outputs a signal with a high voltage amplitude. The signal line driving circuit receives a lower supply voltage and has a low-threshold transistor. With the above configuration, a signal can be transmitted at a high speed with a low voltage amplitude and low power consumption. Thus, the semiconductor circuit device including the signal line driving circuit can reduce operating current and can be operated with a low amplitude and low standby current at a high speed.

Claims

1. A semiconductor circuit device comprising:

a logic circuit for producing a logical output signal; and

a driving circuit for driving a signal line in response to the logical output signal,

wherein the logic circuit is given a first positive voltage and a first negative voltage and includes a first logic transistor of a first conductive type and a second logic transistor of a second conductive type inverse to the first conductive type and connected to the first logic transistor to produce the logical output signal from a point of connection between the first and the second logic transistors; and

the driving circuit comprising;

a first driving transistor of the first conductive type for defining a first logic level; and

a second driving transistor of the second conductive type for defining a second logic level,

wherein at least one of the first and the second driving transistors is given an electric voltage different from at least one of the first positive and the first negative voltages; and

said at least one of the first and the second driving transistors has a threshold level different from that of a same conductive type transistor selected from the first and the second logic transistors,

further wherein the first driving transistor is selected as the at least one of the first and the second driving transistors which is supplied with the electric voltage lower than the first positive voltage (Vcc) and which has the threshold level smaller than that of the first logic transistor in the logic circuit.

2. A semiconductor device as claimed in claim 1, wherein the first logic transistor comprises a PMOS transistor supplied with the first positive voltage (Vcc) and the second logic transistor comprises an NMOS transistor given a ground potential as the first negative voltage.

3. A semiconductor circuit device comprising:

a logic circuit for producing a logical output signal; and

a driving circuit for driving a signal line in response to the logical output signal,

wherein the logic circuit is given a first positive voltage and a first negative voltage and includes a first logic transistor of a first conductive type and a second logic transistor of a second conductive type inverse to the first conductive type and connected to the first logic transistor to produce the logical output signal from a point of connection between the first and the second logic transistors; and

the driving circuit comprising;

a first driving transistor of the first conductive type for defining a first logic level; and

a second driving transistor of the second conductive type for defining a second logic level,

wherein at least one of the first and the second driving transistors is given an electric voltage different from at least one of the first positive and the first negative voltages; and

said at least one of the first and the second driving transistors has a threshold level different from that of a same conductive type transistor selected from the first and the second logic transistors,

wherein the second driving transistor is selected as the at least one of the first and the second driving transistors which is supplied with the electric voltage different from the ground potential.

4. A semiconductor circuit device as claimed in claim 3, wherein the first logic transistor comprises a PMOS transistor supplied with the first positive voltage (Vcc) and the second logic transistor comprises an NMOS transistor given a ground potential as the first negative voltage.

5. A semiconductor circuit device comprising:

a logic circuit for producing a logical output signal; and

a driving circuit for driving a signal line in response to the logical output signal,

wherein the logic circuit is given a first positive voltage and a first negative voltage and includes a first logic transistor of a first conductive type and a second logic transistor of a second conductive type inverse to the first conductive type and connected to the first logic transistor to produce the logical output signal from a point of connection between the first and the second logic transistors; and

the driving circuit comprising;

a first driving transistor of the first conductive type for defining a first logic level; and

a second driving transistor of the second conductive type for defining a second logic level,

wherein at least one of the first and the second driving transistors is given an electric voltage different from at least one of the first positive and the first negative voltages; and

said at least one of the first and the second driving transistors has a threshold level different from that of a same conductive type transistor selected from the first and the second logic transistors,

wherein both the first and the second driving transistors are selected as the at least one of the first and the second driving transistors given source voltages different from the first positive voltage and the first negative voltage, respectively, and having threshold levels different from those of the first and the second logic transistors, respectively.

6. A semiconductor circuit device as claimed in claim 5, wherein the first logic transistor comprises a PMOS transistor supplied with the first positive voltage (Vcc) and the second logic transistor comprises an NMOS transistor given a ground potential as the first negative voltage.

7. A semiconductor circuit device comprising:

a logic circuit which is supplied with a first potential from a positive power supply and with a ground potential from a negative power supply; and

a signal line driving circuit that is supplied from a positive power supply with a second potential lower than the first potential and with a ground potential from a negative power supply;

the signal line driving circuit including;

a PMOS transistor which has a threshold level (represented by an absolute value) lower than that of a PMOS transistor included in the logic circuit and;

an NMOS transistor which has a normal threshold level equivalent with that of an NMOS transistor included in the logic circuit;

the signal line driving circuit buffering an output signal of the logic circuit to send it to a signal line.

8. A semiconductor circuit device as claimed in claim 7, wherein a potential difference between the first potential and the second potential is determined in relation to a threshold difference between the normal threshold level and the lower threshold level and falls within a range from one to ten times of the threshold difference.

9. A semiconductor circuit device comprising:

a logic circuit which is supplied with a first potential from a positive power supply and a ground potential from a negative power supply; and

a signal line driving circuit that is supplied from a positive power supply with the first potential and from a negative power supply with a second potential higher than the ground potential;

the signal line driving circuit including;

an NMOS transistor which has a threshold level lower than that of an NMOS transistor included in the logic circuit; and

a PMOS transistor which has a normal threshold level equivalent with that of a PMOS transistor included in the logic circuit;

the signal line driving circuit buffering an output signal of the logic circuit to send it to a signal line.

10. A semiconductor circuit device as claimed in claim 9, wherein a potential difference between the ground potential and the second potential is determined in relation to a threshold difference between the normal threshold level and the lower threshold level and falls within a range from one to ten times of the threshold potential difference.

11. A semiconductor circuit device comprising:

a logic circuit which is supplied with a first potential from a positive power supply and a ground potential from a negative power supply; and

a signal line driving circuit that is supplied from a positive power supply with a second potential lower than the first potential and from a negative power supply with a third potential higher than the ground potential;

the signal line driving circuit including;

a PMOS transistor which has a threshold level (represented by an absolute value) lower than that of a PMOS transistor included in the logic circuit; and

an NMOS transistor which has a threshold level lower than that of an NMOS transistor included in the logic circuit;

the signal line driving circuit buffering an output signal of the logic circuit to send it to a signal line.

12. A semiconductor circuit device as claimed in claim 11, wherein a potential difference between the first potential and the second electric potential is determined in relation to a threshold difference between the normal threshold level and the lower threshold level and falls within a range from one to ten times of the threshold potential difference.

13. A semiconductor circuit device as claimed in claim 11, wherein a potential difference between the ground potential and the third potential is determined in relation to a threshold difference between the normal threshold level and the lower threshold level and falls within a range from one to ten times of the threshold difference.

14. A semiconductor circuit device comprising:

a logic circuit which is supplied with a first potential from a positive power supply and a ground potential from a negative power supply; and

a signal line driving circuit that is supplied from a first positive supply with the first potential and from a second positive supply with a second potential lower than the first potential;

the signal line driving circuit comprising;

a first switch element arranged between the first power supply and a first node;

a second switch element arranged between the second power supply and the first node, the first and the second switch elements being complementarily turned on or off;

a capacitor connected to the first node;

a PMOS transistor between the first node and a signal line; and

an NMOS transistor between the signal line and the ground potential;

the first switch element being turned off while the second switch element is turned on when the PMOS transistor is kept in an on-state and the NMOS transistor is kept in an off-state;

the first switch element being turned on while the second switch element is turned off when the PMOS transistor is kept in an off-state and the NMOS transistor is kept in an on-state.

15. A semiconductor circuit device as claimed in claim 14, wherein the capacitor has a capacitance determined by multiplying a line capacitance value on the signal line by a value obtained by dividing the second potential by a potential difference between the first and the second electric potentials.