Apparatus and method for phase lock loop gain control using unit current sources

• US 7,224,234 B2
• Filed: 12/21/2005
• Issued: 05/29/2007
• Est. Priority Date: 03/20/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gomez, Ramon A.
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US11/314,618
• Publication Number:
  US 20060097797A1
• Time in Patent Office: 524 Days
• Field of Search: 331/117.R, 331/177.V, 331/179, 331/16, 331/17, 331/2
• US Class Current: 331/16
• CPC Class Codes: H03B 2200/0046 including measures to switch the gain of an amplifier
• CPC Class Codes: H03B 2200/0048 including measures to switch the frequency band, e.g. by harmonic selection
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2201/02 Varying the frequency of the oscillations by electronic means
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1278 the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 5/244 using electronic means
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1072 : by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for-changing PLL operating conditions, in addition to compensating for variable VCO gain.

Claims

1. A method of adjusting a signal frequency of a voltage controlled oscillator (VCO) in a radio frequency (RF) device, comprising:

selecting an oscillator of a plurality of oscillators within the VCO;

selecting a gain cell of a plurality of gain cells based on the selected oscillator, the selected gain cell contributing to a charge pump current;

inputting a first signal that is a function of a reference signal;

inputting a second signal that is a function of a VCO signal;

comparing the first signal and the second signal;

selectively switching one or more capacitors into or out of an LC circuit that is operatively coupled to the VCO, the selective switching being based on the comparison of the first signal and the second signal; and

selectively activating a group of a plurality of groups of current sources within the selected gain cell based on the selectively switched one or more capacitors, the selectively activated group contributing to the charge pump current.

2. The method according to claim 1, wherein the LC circuit comprises a plurality of capacitors in a parallel configuration.

3. The method according to claim 2,

wherein the plurality of capacitors are operatively coupled to a plurality of switches, each capacitor being operatively coupled to a respective switch, and

wherein the respective switch switches the corresponding capacitor into or out of the LC circuit.

4. The method according to claim 3, comprising:

controlling the plurality of switches using a digital control signal.

5. The method according to claim 1,

wherein the VCO comprises a first transistor and a second transistor,

wherein an output of the first transistor is operatively coupled to an input of the second transistor, and

wherein an output of the second transistor is operatively coupled to an input of the first transistor.

6. The method according to claim 5,

wherein the LC circuit comprises a first diode and a second diode,

wherein the first diode and the second diode are in series and are operatively coupled between the output of the first transistor and the output of the second transistor.

7. The method according to claim 6,

wherein the first diode comprises a first varactor diode, and

wherein the second diode comprises a second varactor diode.

8. The method according to claim 7, wherein the first diode and the second diode are operatively coupled such that a forward-bias current path of the first diode is opposite in direction to a forward-bias current path of the second diode.

9. The method according to claim 1, wherein the VCO is part of a phase lock loop (PLL) circuit.

10. The method according to claim 9, wherein the VCO signal is an output signal of the PLL circuit.

11. The method according to claim 9, wherein the PLL circuit comprises a window comparator.

12. The method according to claim 9, wherein the PLL circuit comprises a frequency divider, a phase detector, a charge pump, a loop filter and the VCO.

13. The method according to claim 12,

wherein the frequency divider is operatively coupled to the phase detector,

wherein the phase detector is operatively coupled to the charge pump,

wherein the charge pump is operatively coupled to the loop filter,

wherein the loop filter is operatively coupled to the VCO, and

wherein the VCO is operatively coupled to the frequency divider.

14. The method according to claim 9, comprising:

keeping a gain of the PLL circuit relatively flat for variations in switched capacitance.

15. The method according to claim 9, comprising:

keeping a gain of the PLL circuit relatively flat for variations in VCO gain.

16. The method according to claim 9, comprising:

keeping a gain of the PLL circuit relatively flat for variations in VCO operating conditions.

17. The method according to claim 1, comprising:

adjusting a frequency of the VCO signal as a function of the selective switching of the one or more capacitors.

18. The method according to claim 1, wherein the VCO is used in a PLL circuit that is used in or with an RF receiver.

19. The method according to claim 18, wherein the PLL circuit is used to provide a downconversion signal to a mixer of the RF receiver.

20. The method according to claim 18, wherein the PLL circuit is used to provide an upconversion signal to a mixer of the RF receiver.

21. The method according to claim 1, wherein the VCO is used in a PLL circuit that is used in or with an RF transmitter.

22. The method according to claim 20, wherein the PLL circuit is used to provide a frequency translation signal in or to the RF transmitter.

23. The method according to claim 20, wherein the PLL circuit provides a local oscillator (LO) signal in or to the RF transmitter.

24. A frequency synthesizer for use in a radio frequency (RF) device, comprising:

a frequency divider;

a phase detector operatively coupled to the frequency divider;

a charge pump operatively coupled to the phase detector;

a loop filter operatively coupled to the charge pump;

a voltage controlled oscillator (VCO) operatively coupled to the loop filter and operatively coupled to the frequency divider, the VCO comprising a plurality of oscillators; and

an LC circuit operatively coupled to the VCO,

wherein the LC circuit comprises a plurality of circuital branches in a parallel configuration,

wherein at least some of the circuital branches each comprises a respective capacitor and a corresponding switch,

wherein the corresponding switch switches the respective capacitor into or out of the LC circuit,

wherein an output signal of the VCO is adjusted in frequency as a function of capacitance that is switched into or out of the LC circuit,

wherein an oscillator of the plurality of oscillators of the VCO is selected to select a particular frequency band,

wherein a gain cell of a plurality of gain cells is selected based on the selected oscillator, the selected gain cell contributing to a charge pump current for use by the charge pump, and

wherein a group of a plurality of groups of current sources within the selected gain cell is selectively activated based on the switched one or more respective capacitors, the selected group contributing to the charge pump current.

25. The frequency synthesizer according to claim 24, wherein at least one of the circuital branches comprises two diodes in a series configuration.

26. The frequency synthesizer according to claim 25, wherein the two diodes are two varactor diodes.

27. The frequency synthesizer according to claim 25, wherein the two diodes are disposed in an opposing bias configuration.

28. The frequency synthesizer according to claim 24, wherein the LC circuit comprises an inductor operatively coupled to a voltage supply.

29. The frequency synthesizer according to claim 24, comprising:

a window comparator.

30. The frequency synthesizer according to claim 24, wherein at least the phase detector, the charge pump, the loop filter and the VCO are part of a phase lock loop (PLL) circuit.

31. The frequency synthesizer according to claim 24, wherein a gain of the PLL circuit is kept relative flat for variations in switched capacitance in the LC circuit.

32. The frequency synthesizer according to claim 24, wherein a gain of the PLL circuit is kept relatively flat for variations in VCO gain.

33. The frequency synthesizer according to claim 24, wherein a gain of the PLL circuit is kept relatively flat for variations in VCO operating conditions.

34. The frequency synthesizer according to claim 24, wherein the switches are digitally controlled.

35. The frequency synthesizer according to claim 24, wherein the VCO is part of a PLL circuit that is used in or with a radio frequency (RF) receiver.

36. The frequency synthesizer according to claim 35, wherein the PLL circuit is used to provide a downconversion signal to a mixer of the RF receiver.

37. The frequency synthesizer according to claim 35, wherein the PLL circuit is used to provide an upconversion signal to a mixer of the RF receiver.

38. The frequency synthesizer according to claim 24, wherein the VCO is part of a PLL circuit that is used in or with an RF transmitter.

39. The frequency synthesizer according to claim 38, wherein the PLL circuit is used to provide a frequency translation signal in or to the RF transmitter.

40. The frequency synthesizer according to claim 38, wherein the PLL circuit provides a local oscillator (LO) signal in or to the RF transmitter.