Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states

• US 7,224,613 B2
• Filed: 08/16/2005
• Issued: 05/29/2007
• Est. Priority Date: 06/27/2001
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Tanaka, Tomoharu, Quader, Khandker N., Fong, Yupin
• Primary Examiner(s): Tran; Andrew Q.
• Application Number:
  US11/205,595
• Publication Number:
  US 20050276101A1
• Time in Patent Office: 651 Days
• Field of Search: 365/185.22, 365/185.18, 365/185.17, 365/185.02, 365/185.03
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

Claims

1. A re-programmable non-volatile memory for storing data, comprising:

an array of charge storage elements on an integrated circuit chip, characterized by values of charge stored in some of the storage elements affecting data read from others of the storage elements due to at least electric field coupling between storage elements, and

a programming circuit on said integrated circuit chip that (1) writes a first set of data as a first set of stored values into a first group of the storage elements, (2) thereafter writes a second set of data as a second set of stored values into a second group of the storage elements, wherein at least some of the stored second set of values affect data read from at least some of the first group of storage elements on account of the field coupling between them, and (3) alters the first set of stored values in a manner to counteract an effect of the second set of stored values on data read from the first group of storage elements at least on account the field coupling between them, without rewritting the second set of data into the second group of the storage elements.

2. The memory of claim 1, wherein the programming circuit alters the first set of stored values by reading the first set of data from the first set of stored values of the first group of storage elements and thereafter rewrites the read first set of data into the first group of storage elements as the altered first set of stored values.

3. The memory of claim 2, wherein the programming circuit rewrites the read first set of data into the first group of storage elements by alternately programming and verifying the charge levels stored on the individual storage elements until individually reaching the read first set of stored values.

4. The memory of claim 3, wherein the programming circuit includes verify flags that are set when the charge levels stored on individual storage elements are verified to have reached preliminary levels, after which a rate of increase of at least one programming voltage decreases.

5. The memory of claim 1, wherein the programming circuit includes a state machine that controls the sequence of writing the first set of data, writing the second set of data and altering the first set of stored values.

6. The memory of claim 1, wherein the storage elements include electrically floating gates wherein the stored values are charge levels stored on the floating gates that affect conduction through memory cells of which the floating gates are a part.

7. The memory of claim 1, wherein the storage elements are part of memory cells arranged in parallel strings with conductive word lines orthogonally extending across the strings over storage elements thereof.

8. The memory of claim 1, wherein the array of charge storage elements is further characterized by the stored values on the second set of storage elements causing a distribution of the first set of stored values of the first group of storage elements to broaden, and wherein the programming circuit alters the first set of stored values by compacting the broadened distribution of the first set of stored values of the first group of storage elements.

9. The memory of claim 8, wherein the programming circuit alters the first set of stored values by reading the first set of data from the first set of stored values of the first group of storage elements and thereafter rewrites the read first set of data into the first group of storage elements as the altered first set of stored values.

10. The memory of claim 1, wherein the programming circuit defines more than two stored values for individual ones of the storage elements, thereby to store more than one bit of data per storage element.

11. The memory of claim 1, wherein the programming circuit alters the first set of stored values in the first group of the storage elements after writing the second set of data into the second set of the storage elements.

12. A non-volatile memory for storing data, comprising:

an array of charge storage elements on an integrated circuit chip, characterized by values of charge stored in some of the storage elements affecting data read from others of the storage elements due to at least electric field coupling between storage elements, and

a programming circuit on said integrated circuit chip that (1) writes a first set of data as a first set of stored values into a first group of the storage elements, (2) thereafter writes a second set of data as a second set of stored values into a second group of the storage elements, wherein at least some of the stored second set of values affect data read from at least some of the first group of storage elements on account of the field coupling between them, and (3) alters the first set of stored values in a manner to counteract an effect of the second set of stored values on data read from the first group of storage elements at least on account the field coupling between them, wherein the programming circuit alters the first set of stored values in the first group of the storage elements before writing the second set of data into the second group of the storage elements.

13. A method of operating a re-programmable non-volatile memory system wherein values stored in some of storage elements of an array of memory elements affect values read from others of the storage elements because of at least electric field coupling between storage elements, comprising:

writing into a first group of storage elements a first set of stored values that correspond to a first set of data,

thereafter writing into a second group of storage elements different from the first group a second set of stored values that correspond to a second set of data, wherein at least some of the stored second set of values affect data read from at least some of the first group of storage elements because of at least field coupling between them, and

in order to facilitate accurate reading of the first set of data from the first group of storage elements, only the first set of stored values written into the first group of storage elements is altered in a manner that counteracts an effect of the second set of stored values on the data read from said at least some of the first group of storage elements because of at least field coupling between them, without re-writing the second group of storage elements.

14. The method of claim 13, wherein a characteristic of the first set of stored values that is affected by the second set of stored values includes broadening an apparent distribution of those of the stored first set of values that correspond to particular states of the first set of data, and wherein altering the first set of stored values includes compacting the distribution of those of the stored first set of values that correspond to particular states of the first set of data.

15. The method of claim 14, wherein compacting the distribution occurs after writing the second set of stored values.

16. The method of claim 15, wherein prior to compacting the distribution of the stored first set of values, the first set of data is read from the first group of storage elements.

17. The method of claim 14, wherein compacting the distribution occurs before writing the second set of stored values.

18. The method of claim 13, wherein altering the first set of stored values includes reading the first set of stored values written into the first group of storage elements and thereafter reprogramming the first group of storage elements with the read data, whereby the reprogramming is accomplished without having to retain a copy of the data initially programmed into the first group of storage elements.

19. The method of claim 13, wherein the stored values are charge levels stored on the charge storage elements in the form of electrically conductive floating gates.

20. The method of claim 13, carried out in a memory system having the memory cells connected in a NAND arrangement.

21. The method of claim 13, wherein more than two ranges of values are defined for individual ones of the charge storage elements in order to store more than one bit of data on the individual ones of the charge storage elements.

22. The method of claim 13, wherein the storage elements are operated to individually have a storage window divided into a plurality of defined ranges of storage levels representative of more than one bit of data and which are separated from one another, and wherein writing stored values into the individual storage elements includes incrementally changing the storage level thereof until one of the storage level ranges is reached that corresponds to the data being stored therein.