System for direct acquisition of received signals

• US 7,224,721 B2
• Filed: 10/11/2002
• Issued: 05/29/2007
• Est. Priority Date: 10/11/2002
• Status: Active Grant

• Current Assignee: Mitre Corporation
• Original Assignee: Mitre Corporation
• Inventors: Capozza, Paul, Fite, John, Betz, John
• Primary Examiner(s): Ha, Dac
• Assistant Examiner(s): Wang, Ted M.
• Application Number:
  US10/269,254
• Publication Number:
  US 20040071200A1
• Time in Patent Office: 1,691 Days
• Field of Search: 375/152, 375/142, 375/143, 375/150, 375/343, 375/350
• US Class Current: 375/152
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: H04B 1/70752 Partial correlation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

Signal processing architectures for direct acquisition of spread spectrum signals using long codes. Techniques are described for achieving a high of parallelism, employing code matched filter banks and other hardware sharing. In one embodiment, upper and lower sidebands are treated as two independent signals with identical spreading codes. Cross-correlators, in preferred embodiments, are comprised of a one or more banks of CMFs for computing parallel short-time correlations (STCs) of received signal samples and replica code sequence samples, and a means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the computed STCs. One or more intermediate quantizers may optionally be disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis. The techniques described may be used with BOC modulated signals or with any signal having at least two distinct sidebands.

Claims

1. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal, comprising:

means for sampling the received DSSS signal at a predetermined sampling rate;

means for cross-correlating, in a parallel fashion, time and frequency shifted versions of the sampled DSSS signal with samples of a locally generated replica of a pseudo random noise (PN) code sequence used to spread the spectrum of the received DSSS signal in order to obtain cross-correlation values;

a Doppler compensator coupled to the cross-correlating means for processing the obtained cross-correlation values in order to compensate for misalignment effects resulting from time-companding of the received DSSS signal;

an integrator for non-coherently integrating groups of the compensated cross-correlation values representing corresponding time and frequency offsets of different time segments of the received signal and replica code sequence in order to obtain correlation metrics; and

a detector for detecting whether a sum of the magnitudes of the correlation metrics exceeds a detection threshold,

wherein the cross-correlating means further comprises;

a bank of code matched filters for computing short-time correlations (STCs) entirely in parallel; and

means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the computed STCs.

2. The SPA of claim 1, wherein the cross-correlating means further comprises one or more intermediate quantizers disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis.

3. The SPA of claim 1, wherein:

the code matched filters compute the STCs for interleaved in-phase (I) and quadrature (Q) components of the sampled DSSS signal in a pipelined fashion, the code matched filters operating at twice the sampling rate; and

each code matched filter has two data shift registers per tap for holding the interleaved components.

4. The SPA of claim 1, wherein:

the DSSS signal has multiple sidebands;

the SPA further comprises means for digitally selecting and resampling two or more of the multiple sidebands;

the cross-correlating means further comprises an interleaver for interleaving data of the re-sampled sidebands;

the code matched filters compute the STCs for the interleaved sideband data in a pipelined fashion; and

each code matched filter has additional data shift registers for holding the interleaved sideband data and operates at a rate equal to the product of the number of selected sidebands and the predetermined sampling rate.

5. The SPA of claim 1, wherein the cross-correlating means further comprises:

means for resampling the received DSSS signal at a rate equal to an integer multiple of the nominal chip rate;

one or more code matched filters having a plurality of multipliers whose required number is divided by the integer multiple; and

wherein each code matched filter'"'"'s associated summing network includes hardware for storing partial sums and adding partial sums from previous clock cycles in computing the cross-correlation values.

6. The SPA of claim 1, wherein the Doppler compensator further comprises:

delay means for applying delays to input streams of cross-correlation values corresponding to frequency-shifted versions of the received DSSS signal and the replica code sequence; and

means for selecting appropriate delays to be applied based upon non-coherent integration counter values.

7. The SPA of claim 6, wherein the means for applying frequency-shifted-dependent delays further comprises:

one or more integer delay line filters;

one or more fractional delay line filters;

a pre-computed lookup table of filter coefficients for use by the integer delay line filters and fractional delay line filters in determining an appropriate delay to be applied; and

means for initializing and updating integer and fractional delay line filter coefficients as a function of externally specified frequency shifts and the non-coherent integration counter values.

19. The SPA of claims 1, 8, 9 or 11, wherein the non-coherent integrator further comprises:

means for controlling relative timing between the replica code sequence and the received signal;

means for realigning the replica code sequence at the start of a new time uncertainty;

means for integrating multiple correlation blocks; and

wherein code sequence segments overlapping in time between groups of cross-correlation values compensate for invalid samples resulting from Doppler compensation, post peak-detection idle time resulting from a peak being detected at the end of a tile, and a change in the number of samples available for processing as a result of code Doppler effects.

20. The SPA of claim 19, wherein the non-coherent integrator further comprises means for:

loading and swapping of code matched filter registers containing consecutive non-contiguous code sequence segments to support the seamless switching between processing multiple blocks of a tile and for controlling the realignment of the received signal to the symbol boundary along with the local reference code when switching time uncertainties;

controlling initiation of a new block for a given time offset during the NCI process;

controlling a signal that distinguishes invalid data from the code Doppler processing and the valid data at the end of the NCI process; and

controlling discarding the unused signal at the end of the NCI processing for a given time uncertainty and coordinating the start of the NCI processing for the next time uncertainty.

21. The SPA of claims 1, 8–

10 or 11, wherein the SPA is implemented in a single ASIC.

22. The SPA of claim 21, wherein off-chip memory is used only to store non-coherent integration results.

23. The SPA of claims 1, 8–

10 or 11, wherein the SPA is implemented in a single FPGA.

24. The SPA of claim 23, wherein off-chip memory is used only to store non-coherent integration results.

25. The SPA of claims 1, 8, 9 or 10, wherein the DSSS signal to be acquired is a binary offset carrier modulated signal.

26. The SPA of claims 1, 8, 9 or 10, wherein the DSSS signal to be acquired is a GPS M-code signal.

8. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal, comprising:

means for sampling the DSSS signal at a predetermined sampling rate;

an interleaver for interleaving in-phase (I) and quadrature (Q) components of the sampled DSSS signal;

one or more code matched filters for correlating in a pipelined fashion time and frequency shifted versions of the interleaved components with samples of a replica of a pseudo random noise (PN) code sequence used to spread the spectrum of the received DSSS signal to obtain cross-correlation outputs, wherein each code matched filter operates at twice the sampling rate and includes two data shift registers per tap for holding the interleaved components;

means for calculating cross-correlation values utilizing discrete-time Fourier analysis of the cross-correlation outputs;

an integrator for non-coherently integrating the cross-correlation values representing corresponding time and frequency offsets of time segments of the received signal and replica code sequence to obtain correlation metrics; and

a detector for detecting whether a sum of the magnitudes of the correlation metrics exceeds a detection threshold.

9. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal having multiple sidebands, comprising:

means for sampling one or more of multiple sidebands at a predetermined sampling rate;

means for digitally selecting and resampling the one or more multiple sidebands;

an interleaver for interleaving data of the re-sampled sidebands;

one or more code matched filters for correlating in a pipelined fashion time and frequency shifted versions of the interleaved sideband data with samples of a replica of a PN code sequence used to spread the spectrum of the received DSSS signal to obtain cross-correlation outputs, the code matched filters each having additional data shift registers for holding the interleaved sideband data and each operating at a rate equal to the product of the number of selected sidebands and the predetermined sampling rate;

means for calculating cross-correlation values utilizing discrete-time Fourier analysis of the cross-correlation outputs;

an integrator for non-coherently integrating the cross-correlation values representing corresponding time and frequency offsets of time segments of the received signal and reference PN code sequence to obtain correlation metrics; and

a detector for detecting whether a sum of the magnitudes of the correlation metrics exceeds a detection threshold.

10. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal having at least two sidebands, comprising:

means for selecting a sideband of the received DSSS signal;

means for down-sampling the selected sideband at a predetermined sampling rate to obtain versions of the selected sideband;

an interleaver for interleaving in-phase (I) and quadrature (Q) components of the versions of the selected sideband;

means for cross-correlating a locally generated sampled replica of a pseudo-random noise (PN) code sequence used to spread the spectrum of the received DSSS signal with time and frequency shifted versions of the selected sideband to obtain cross-correlation values, wherein the cross-correlating means includes at least one of (i)–

(vi);

(i) means for re-sampling each selected sideband at a rate equal to an integer multiple of the nominal chip rate;

(ii) a bank of code matched filters for computing short-time correlation (STCs) for the interleaved sideband components in a pipelined fashion, each code matched filter having a plurality of data shift registers per tap for holding the interleaved sideband components and operating at a rate equal to the product of twice the number of sampled sidebands and the predetermined sampling rate;

(iii) a bank of code matched filters for computing short-time correlations (STCs) entirely in parallel;

(iv) one or more code matched filters having a plurality of multipliers whose required number is divided by the integer multiple, wherein each code matched filter'"'"'s associated summing network has a hardware means for storing partial sums and adding partial sums from previous clock cycles in computing the cross-correlation values;

(v) means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the STCs; and

(vi) one or more intermediate quantizers disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis;

a Doppler compensator coupled to the cross-correlating means for processing the obtained cross-correlation values in order to compensate for misalignment effects resulting from time-companding of the received DSSS signal, wherein the Doppler compensator includes at least one of(a)–

(d);

(a) one or more integer delay line filters for coarse Doppler frequency dependent compensation;

(b) one or more fractional delay line filters for fine Doppler frequency dependent compensation;

(c) a table of filter coefficients for use by the fractional delay line filters in finely resolving Doppler frequency-dependent delays; and

(d) externally controllable settings for applying the appropriate integer and fractional delays to each cross-correlation value; and

a detector for detecting whether the magnitude of the cross-correlation values exceeds a detection threshold.

11. A signal processing architecture (SPA) for acquiring a received multiband input signal comprising:

means for selecting multiple sidebands from the received multiband input signal;

means for down-sampling each selected sideband at a predetermined sampling rate to obtain versions of each selected sideband;

an interleaver for interleaving in-phase (I) and quadrature (Q) components of the versions of each selected sideband;

means for cross-correlating a replica of a pseudo random noise (PN) code sequence used to spread the spectrum of the received signal with time and frequency shifted versions of each selected sideband to obtain cross-correlation values, wherein the cross-correlating means further comprises a bank of code matched filters for computing short-time correlations (STCs) for the interleaved sideband components in a pipelined fashion, each code matched filter having a plurality of data shift registers per tap for holding the interleaved components and operating at a rate equal to the product of twice the number of sampled sidebands and the predetermined sampling rate;

an integrator for non-coherently combining the cross-correlation values to obtain correlation metrics; and

a detector for detecting whether the magnitudes of the correlation metrics exceed a detection threshold.

12. The SPA of claim 11, further comprising:

one or more intermediate quantizers for independently quantizing the versions of each selected sideband; and

circuitry for controlling a loading factor of the quantizing means.

13. The SPA of claim 12, wherein the loading factor control circuitry is an AGC like circuit.

14. The SPA of claim 11, wherein the cross-correlating means further comprises:

a bank of code matched filters for computing short-time correlations (STCs) entirely in parallel; and

means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the STCs.

15. The SPA of claim 14, wherein the cross-correlating means further comprises:

one or more intermediate quantizers disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis.

16. The SPA of claim 11, wherein the cross-correlating means further comprises:

means for resampling each selected sideband at a rate equal to an integer multiple of the nominal chip rate;

one or more code matched filters having a plurality of multipliers whose required number is divided by the integer multiple; and

wherein each code matched filter'"'"'s associated summing network has a hardware means for storing partial sums and adding partial sums from previous clock cycles in computing the cross-correlation values.

17. The SPA of claim 11, further comprising:

Doppler compensator coupled to the cross-correlating means for processing the obtained cross-correlation values in order to compensate for misalignment effects resulting from time-companding of the received DSSS signal.

18. The SPA of claim 17, wherein the Doppler compensator further comprises:

one or more integer delay line filters for coarse Doppler frequency dependent compensation;

one or more fractional delay line filters for fine Doppler frequency dependent compensation;

a table of filter coefficients for use by the fractional delay line filters in finely resolving Doppler frequency-dependent delays; and

externally controllable settings for applying the appropriate integer and fractional delays to each cross-correlation value.

27. A cross-correlation apparatus for cross-correlating a sampled reference signal with time and frequency shifted samples of a received signal that was sampled at a predetermined sampling rate, comprising:

an interleaver for interleaving in-phase (I) and quadrature (Q) components of the sampled received signal;

a bank of code matched filters for computing short-time correlations (STCs) for the interleaved components in a pipelined fashion, the code matched filters operating at twice the predetermined sampling rate and each having two data shift registers per tap for holding the interleaved components; and

means for calculating cross-correlation values utilizing discrete-time Fourier analysis of the STCs.

28. A cross-correlation apparatus for cross-correlating a sampled reference signal with time and frequency shifted samples of a received signal having multiple sidebands one or more of which were sampled at a predetermined sampling rate, comprising:

means for digitally selecting and resampling one or more of the multiple sidebands;

an interleaver for interleaving data components of the one or more re-sampled sidebands;

a bank of code matched filters for computing short-time correlations (STCs) for the interleaved sideband data in a pipelined fashion, each code matched filter having additional data shift registers for holding the interleaved sideband data and operating at a rate equal to the product of the number of selected sidebands and the predetermined sampling rate; and

means for calculating cross-correlation values utilizing discrete-time Fourier analysis of the STC outputs.

29. A cross-correlation apparatus for cross-correlating a sampled pseudo random noise (PN) code reference signal with time and frequency shifted samples of a received signal, comprising:

means for resampling the received signal at a rate equal to an integer multiple of the nominal chip rate;

a bank of code matched filters for computing short-time correlations (STCs) in a parallel fashion of the re-sampled received signal and sampled reference signal, each code matched filter having a plurality of multipliers whose required number is divided by the integer multiple; and

wherein each code matched filter'"'"'s associated summing network has a hardware for storing partial sums and adding partial sums from previous clock cycles to compute cross-correlation values.

30. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal, comprising:

means for sampling the received DSSS signal at a predetermined sampling rate;

means for cross-correlating, in a parallel fashion, time and frequency shifted versions of the sampled DSSS signal with samples of a locally generated replica of a pseudo random noise (PN) code sequence used to spread the spectrum of the received DSSS signal in order to obtain cross-correlation values;

a Doppler compensator coupled to the cross-correlating means for processing the obtained cross-correlation values in order to compensate for misalignment effects resulting from time-companding of the received DSSS signal;

an integrator for non-coherently integrating groups of the compensated cross-correlation values representing corresponding time and frequency offsets of different time segments of the received signal and replica code sequence in order to obtain correlation metrics; and

a detector for detecting whether a sum of the magnitudes of the correlation metrics exceeds a detection threshold,

wherein the Doppler compensator further comprises;

delay means for applying delays to input streams of cross-correlation values corresponding to frequency-shifted versions of the received DSSS signal and the replica code sequence; and

means for selecting appropriate delays to be applied based upon non-coherent integration counter values.

31. The SPA of claim 30, wherein the cross-correlating means further comprises:

a bank of code matched filters for computing short-time correlations (STCs) entirely in parallel; and

means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the computed STCs.

32. The SPA of claim 31, wherein the cross-correlating means further comprises one or more intermediate quantizers disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis.

33. The SPA of claim 31, wherein:

the code matched filters compute the STCs for interleaved in-phase (I) and quadrature (Q) components of the sampled DSSS signal in a pipelined fashion, the code matched filters operating at twice the sampling rate; and

each code matched filter has two data shift registers per tap for holding the interleaved components.

34. The SPA of claim 31, wherein:

the DSSS signal has multiple sidebands;

the SPA further comprises means for digitally selecting and resampling two or more of the multiple sidebands;

the cross-correlating means further comprises an interleaver for interleaving data of the re-sampled sidebands;

the code matched filters compute the STCs for the interleaved sideband data in a pipelined fashion; and

each code matched filter has additional data shift registers for holding the interleaved sideband data and operates at a rate equal to the product of the number of selected sidebands and the predetermined sampling rate.

35. The SPA of claim 31 wherein the cross-correlating means further comprises:

means for resampling the received DSSS signal at a rate equal to an integer multiple of the nominal chip rate;

one or more code matched filters having a plurality of multipliers whose required number is divided by the integer multiple; and

wherein each code matched filter'"'"'s associated summing network includes hardware for storing partial sums and adding partial sums from previous clock cycles in computing the cross-correlation values.

36. The SPA of claim 30, wherein the means for applying frequency-shifted-dependent delays further comprises:

one or more integer delay line filters;

one or more fractional delay line filters;

a pre-computed lookup table of filter coefficients for use by the integer delay line filters and fractional delay line filters in determining an appropriate delay to be applied; and

means for initializing and updating integer and fractional delay line filter coefficients as a function of externally specified frequency shifts and the non-coherent integration counter values.

37. A signal processing architecture (SPA) for acquiring a received direct sequence spread spectrum (DSSS) signal, comprising:

means for sampling the received DSSS signal at a predetermined sampling rate;

means for cross-correlating, in a parallel fashion, time and frequency shifted versions of the sampled DSSS signal with samples of a locally generated replica of a pseudo random noise (PN) code sequence used to spread the spectrum of the received DSSS signal in order to obtain cross-correlation values;

a Doppler compensator coupled to the cross-correlating means for processing the obtained cross-correlation values in order to compensate for misalignment effects resulting from time-companding of the received DSSS signal;

an integrator for non-coherently integrating groups of the compensated cross-correlation values representing corresponding time and frequency offsets of different time segments of the received signal and replica code sequence in order to obtain correlation metrics; and

a detector for detecting whether a sum of the magnitudes of the correlation metrics exceeds a detection threshold,

wherein the cross-correlating means further comprises;

a bank of code matched filters for computing short-time correlations (STCs) entirely in parallel; and

means for calculating the cross-correlation values utilizing discrete-time Fourier analysis of the computed STCs; and

wherein the Doppler compensator further comprises;

delay means for applying delays to input streams of cross-correlation values corresponding to frequency-shifted versions of the received DSSS signal and the replica code sequence; and

means for selecting appropriate delays to be applied based upon non-coherent integration counter values.

38. The SPA of claim 37, wherein the cross-correlating means further comprises one or more intermediate quantizers disposed between the bank of code matched filters and the cross-correlation calculation means for reducing word-sizes of the STCs prior to Fourier analysis.

39. The SPA of claim 37, wherein:

the code matched filters compute the STCs for interleaved in-phase (I) and quadrature (Q) components of the sampled DSSS signal in a pipelined fashion, the code matched filters operating at twice the sampling rate; and

each code matched filter has two data shift registers per tap for holding the interleaved components.

40. The SPA of claim 37, wherein:

the DSSS signal has multiple sidebands;

the SPA further comprises means for digitally selecting and resampling two or more of the multiple sidebands;

the cross-correlating means further comprises an interleaver for interleaving data of the re-sampled sidebands;

the code matched filters compute the STCs for the interleaved sideband data in a pipelined fashion; and

each code matched filter has additional data shift registers for holding the interleaved sideband data and operates at a rate equal to the product of the number of selected sidebands and the predetermined sampling rate.

41. The SPA of claim 37 wherein the cross-correlating means further comprises:

means for resampling the received DSSS signal at a rate equal to an integer multiple of the nominal chip rate;

one or more code matched filters having a plurality of multipliers whose required number is divided by the integer multiple; and

wherein each code matched filter'"'"'s associated summing network includes hardware for storing partial sums and adding partial sums from previous clock cycles in computing the cross-correlation values.

42. The SPA of claim 37, wherein the means for applying frequency-shifted-dependent delays further comprises:

one or more integer delay line filters;

one or more fractional delay line filters;

a pre-computed lookup table of filter coefficients for use by the integer delay line filters and fractional delay line filters in determining an appropriate delay to be applied; and

means for initializing and updating integer and fractional delay line filter coefficients as a function of externally specified frequency shifts and the non-coherent integration counter values.