High-speed wide bandwidth data detection circuit
First Claim
1. A high-speed, wide bandwidth data detection circuit comprises:
- phase detection module operably coupled to produce controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock;
data detection module operably coupled to produce the detected data based on the incoming data stream and the recovered clock;
loop filter operably coupled to convert the controlled current into a control voltage;
voltage controlled oscillator operably coupled to convert the control voltage into the recovered clock; and
wherein the phase detection module comprises;
a first differential exclusive OR gate operably coupled to produce a first differential current component of the controlled current based on a first representation of the incoming data stream and a second representation of the incoming data stream;
a second differential exclusive OR gate operably coupled to produce a second differential current component of the controlled current based on a third representation of the incoming data stream and a fourth representation of the incoming data stream;
a first current source module operably coupled to provide a first reference current;
a second current source module operably coupled to provide a second reference current; and
a differential common gate amplifier circuit operably coupled to the first and second differential exclusive OR gates and to the first and second current source modules, wherein the differential common gate amplifier circuit produces a differential controlled current based on the first and second differential current components and the first and second reference currents.
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Accused Products
Abstract
A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.
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Citations
25 Claims
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1. A high-speed, wide bandwidth data detection circuit comprises:
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phase detection module operably coupled to produce controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock; data detection module operably coupled to produce the detected data based on the incoming data stream and the recovered clock; loop filter operably coupled to convert the controlled current into a control voltage; voltage controlled oscillator operably coupled to convert the control voltage into the recovered clock; and wherein the phase detection module comprises; a first differential exclusive OR gate operably coupled to produce a first differential current component of the controlled current based on a first representation of the incoming data stream and a second representation of the incoming data stream; a second differential exclusive OR gate operably coupled to produce a second differential current component of the controlled current based on a third representation of the incoming data stream and a fourth representation of the incoming data stream; a first current source module operably coupled to provide a first reference current; a second current source module operably coupled to provide a second reference current; and a differential common gate amplifier circuit operably coupled to the first and second differential exclusive OR gates and to the first and second current source modules, wherein the differential common gate amplifier circuit produces a differential controlled current based on the first and second differential current components and the first and second reference currents. - View Dependent Claims (2, 3, 4)
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5. A method for high-speed wide bandwidth data detection, the method comprises:
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producing a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock; producing detected data based on the incoming data stream and the recovered clock; converting the controlled current into a control voltage; converting the control voltage into the recovered clock; and wherein producing the controlled current includes, exclusive ORing a first representation of the incoming data stream and a second representation of the incoming data stream to produce a first differential current component of the controlled current; exclusive ORing a third representation of the incoming data stream and a fourth representation of the incoming data stream to produce a second differential current component of the controlled current; generating a first reference current; generating a second reference current; and producing a differential controlled current based on the first and second differential current components and the first and second reference currents. - View Dependent Claims (6)
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7. An apparatus for high-speed wide bandwidth data detection, the apparatus comprises:
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processing module; memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to; produce a controlled current based on a current mode mathematical manipulation of differences between the incoming data stream and a recovered clock; produce detected data based on the incoming data stream and the recovered clock; convert the controlled current into a control voltage; and convert the control voltage into the recovered clock; and wherein the memory further comprises operational instructions that cause the processing module to generate the controlled current by; exclusive ORing a first representation of the incoming data stream and a second representation of the incoming data stream to produce a first differential current component of the controlled current; exclusive ORing a third representation of the incoming data stream and a fourth representation of the incoming data stream to produce a second differential current component of the controlled current; generating a first reference current; generating a second reference current; and producing a differential controlled current based on the first and second differential current components and the first and second reference currents. - View Dependent Claims (8)
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9. A high-speed, wide bandwidth data detection circuit comprises:
primary locked loop operably coupled to process an incoming data stream to produce detected data and a recovered clock, wherein the primary locked loop includes; phase detection module operably coupled to produce controlled current based on a current mode mathematical manipulation of differences between the incoming data stream and the recovered clock, wherein, when the primary locked loop is in an idle state, the phase detection module produces a substantially zero controlled current, and when the primary locked loop transitions from the idle state to an active state, the phase detection module produces the controlled current in a known manner; data detection module operably coupled to produce the detected data based on the incoming data stream and the recovered clock;
loop filter operably coupled to convert the controlled current into a control voltage;voltage controlled oscillator operably coupled to convert the control voltage into the recovered clock; secondary locked loop operably coupled to provide an initial coarse locking for the primary locked loop when the primary locked loop is in the idle state; and state transition module operably coupled to place the primary locked loop in the idle state and the secondary locked loop in the active state and to switch the primary locked loop from the idle state to the active state and to switch the second locked loop from the active state to the idle state during non-updating periods of the phase detection module. - View Dependent Claims (10, 11, 12)
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13. A method for high-speed, wide bandwidth data detection, the method comprises:
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generating an initial coarse locking based on a reference signal and a feedback signal during an idle mode of operation; generating a substantially zero controlled current during the idle mode of operation;
when the initial coarse locking is achieved, switching from the idle mode of operation to an active mode of operation;when in the active mode of operation;
producing a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock, wherein transition from the substantially zero controlled current to the controlled current is done in a known manner;producing detected data based on the incoming data stream and the recovered clock;
converting the controlled current into a control voltage;converting the control voltage into the recovered clock; and wherein the memory further comprises operational instructions that cause the processing module to;
transitioning from the idle mode of operation to the active mode of operation during non-updating periods of the generating of the controlled current and of the generating of the substantially zero controlled current. - View Dependent Claims (14, 15, 16)
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17. An apparatus for high-speed, wide bandwidth data detection, the apparatus comprises:
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processing module; memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to; generate an initial coarse locking based on a reference signal and a feedback signal during an idle mode of operation; generate a substantially zero controlled current during the idle mode of operation; when the initial coarse locking is achieved, switch from the idle mode of operation to an active mode of operation; when in the active mode of operation; produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock, wherein transition from the substantially zero controlled current to the controlled current is done in a known manner; produce detected data based on the incoming data stream and the recovered clock; convert the controlled current into a control voltage; convert the control voltage into the recovered clock; wherein the memory further comprises operational instructions that cause the processing module to;
transition from the idle mode of operation to the active mode of operation during non-updating periods of the generating of the controlled current and of the generating of the substantially zero controlled current. - View Dependent Claims (18, 19, 20)
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21. A high-speed, wide bandwidth data detection circuit comprises:
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phase detection module operably coupled to produce primary controlled current based on a current mode mathematical manipulation of phase differences between the incoming data stream and a recovered clock when fine loop operation is enabled; data detection module operably coupled to produce the detected data based on the incoming data stream and the recovered clock; frequency detector operably coupled to produce a frequency difference signal based on frequency differences between a reference signal and a feedback signal when coarse loop operation is enabled; charge pump operably coupled to convert the frequency difference signal into a secondary controlled current when the coarse loop operation is enabled; loop filter operably coupled to convert the primary controlled current or the secondary controlled current into a control voltage; common mode feedback circuit operably coupled to the loop filter to provide a common mode reference for the primary and secondary controlled currents; voltage controlled oscillator operably coupled to convert the control voltage into the recovered clock when the fine loop operation is enabled and to convert the control voltage into an intermediate clock when the coarse loop operation is enabled; and divider module operably coupled to produce the feedback signal based on the intermediate clock and a divider value. - View Dependent Claims (22, 23, 24)
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25. A phase detection module comprising:
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first current mode logic circuit operably coupled to perform a first portion of a current mode mathematical manipulation on phase differences between an incoming data stream and a recovered clock to produce a first differential current component of a controlled current, the first current mode logic circuit including, a first differential exclusive OR gate operably coupled to produce the first differential current component of the controlled current based on a first representation of the incoming data stream and a second representation of the incoming data stream; and a first current source module operably coupled to provide a first reference current; second current mode logic circuit operably coupled to perform a second portion of the current mode mathematical manipulation on transition differences between the incoming data stream and the recovered clock to produce a second differential current component of the controlled current, the second current mode logic circuit including, a second differential exclusive OR gate operably coupled to produce the second differential current component of the controlled current based on a third representation of the incoming data stream and a fourth representation of the incoming data stream; and a second current source module operably coupled to provide a second reference current; and a differential common gate amplifier circuit operably coupled to the first and second differential exclusive OR gates and to the first and second current source modules, wherein the differential common gate amplifier circuit produces a differential controlled current based on the first and second differential current components and the first and second reference currents.
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Specification