PMA RX in coarse loop for high speed sampling
First Claim
1. A transceiver for processing high data rate serial data, comprising:
- phase-locked loop circuitry further including selectable coarse loop PLL and selectable fine loop PLL circuits, the selectable coarse loop PLL for producing a coarse loop synchronized oscillation signal based on a reference clock, the coarse loop synchronized oscillation signal having a specified degree of accuracy relative to a received serial data rate and the selectable fine loop PLL for adjusting the coarse loop synchronized oscillation signal in phase coherence with the received high data rate serial data; and
mode determination logic coupled to produce mode switching signals to selectively switch the selectable coarse loop PLL and selectable fine loop PLL into and out of coupling according to defined operational logic within the mode determination logic.
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Abstract
A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
17 Citations
13 Claims
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1. A transceiver for processing high data rate serial data, comprising:
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phase-locked loop circuitry further including selectable coarse loop PLL and selectable fine loop PLL circuits, the selectable coarse loop PLL for producing a coarse loop synchronized oscillation signal based on a reference clock, the coarse loop synchronized oscillation signal having a specified degree of accuracy relative to a received serial data rate and the selectable fine loop PLL for adjusting the coarse loop synchronized oscillation signal in phase coherence with the received high data rate serial data; and mode determination logic coupled to produce mode switching signals to selectively switch the selectable coarse loop PLL and selectable fine loop PLL into and out of coupling according to defined operational logic within the mode determination logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification