Method, system and medium for controlling semiconductor wafer processes using critical dimension measurements

• US 7,225,047 B2
• Filed: 03/19/2002
• Issued: 05/29/2007
• Est. Priority Date: 03/19/2002
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Foad, Majeed, Adibi, Babak, Somekh, Sasson, Al-Bayati, Amir
• Primary Examiner(s): Paladini; Albert W.
• Assistant Examiner(s): SHECHTMAN, SEAN P
• Application Number:
  US10/100,184
• Publication Number:
  US 20030180972A1
• Time in Patent Office: 1,897 Days
• Field of Search: 700109-110, 700/117, 700119-121, 438/5, 438/14, 702 81- 84
• US Class Current: 700/121
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Methods, systems, and mediums of controlling a semiconductor manufacturing process are described. The method comprises the steps of measuring at least one critical dimension of at least one device being fabricated on at least one of the plurality of wafers, determining at least one process parameter value on the at least one measured dimension, and controlling at least one semiconductor manufacturing tool to process the at least one of the plurality of wafers based on the at least one parameter value. A variation in the at least one critical dimension causes undesirable variations in performance of the at least one device, and at least one process condition is directed to controlling the processing performed on the plurality of wafers. The at least one manufacturing tool includes at least one of an implanter tool and an annealing tool.

Claims

1. A method of processing a plurality of wafers for manufacturing semiconductor devices, the method sequentially comprising:

(a) measuring at least one critical dimension of at least one device fabricated on at least one of the plurality of wafers by a metrology tool of an implant-annealing process module before the at least one of the plurality of wafers has been processed in at least one implant or annealing processing tool of the implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

(b) determining at least one control parameter value of the at least one implant or annealing processing tool based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an energy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level;

(c) controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value;

(d) measuring at least one post process dimension of the at least one of the plurality of wafers after step (c), wherein the measured at least one post process dimension is different than the measured at least one critical dimension;

(e) determining whether the measured at least one post process dimension is within a first predetermined range; and

(f) adjusting the at least one implant or annealing processing tool of the implant-annealing process module upon determining that the measured at least one post process dimension is not within the first predetermined range.

2. The method of claim 1, wherein the at least one post process dimension is a junction depth and the method further comprises:

(g) sending the at least one of the plurality of wafers to a next processing tool upon determining that the at least one post process dimension is within the first predetermined range.

3. The method of claim 1 wherein the at least one critical dimension is a gate length.

4. The method of claim 1, wherein the at least one implant or annealing processing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay.

5. The method of claim 4, wherein the at least one implanter tool is a beamline type implanting tool.

6. The method of claim 1, wherein the first predetermined range is plus or minus 10 percent from a respective target value.

7. The method of claim 1, further comprising:

forming the at least one critical dimension prior to measuring at least one critical dimension.

8. The method of claim 4, wherein the at least one implanter tool processes one wafer at a time.

9. The method of claim 1, wherein the at least one implant or annealing processing tool includes at least one annealing tool for at least reducing deviation in gate delay.

10. The method of claim 9, wherein the annealing tool is controlled by parameters that include at least one of a Rapid Thermal Processing (RTP) peak temperature level and anneal time length.

11. An implant-annealing process module comprising:

a first metrology tool configured to measure at least one critical dimension of at least one device fabricated on at least one of a plurality of wafers before the at least one of the plurality of wafers is processed by at least one implant or annealing processing tool of the implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

a module controller configured to determine at least one control parameter value of the implant or annealing processing tool based on the measured at least one critical dimension, wherein the at least one implant or annealing processing tool of the implant-annealing process module is configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one control parameter value and wherein the at least one control parameter value determined by the module controller is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an enemy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level; and

a second metrology tool configured to measure at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is different from the at least one critical dimension and wherein the module controller is further configured to determine whether the measured at least one post process dimension is within a first predetermined range and the module controller is further configured to adjust the at least one implant or annealing processing tool of the implant-annealing process module upon determining that the measured at least one post process dimension is not within the first predetermined range.

12. The implant-anneallng process module of claim 11 wherein the at least one post process dimension is junction depth.

13. The implant-annealing process module of claim 11 wherein the module controller is further configured to adjust at least one parameter value to re-process the at least one of the plurality of wafers when the measured at least one post process dimension is not within the first predetermined range and configured to cause the at least one of the plurality of wafers to be sent to a next processing tool upon determining that the measured at least one post process dimension is within the first predetermined range.

14. The implant-annealing process module of claim 11 wherein the first metrology tool is further configured to measure a length of a gate of at least one device fabricated on the at least one of the plurality of wafers.

15. The implant-annealing process module of claim 11, wherein the at least one implant or annealing processing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay.

16. The implant-annealing process module of claim 15, wherein the at least one Implanting tool is a beamline type implanting tool.

17. The implant-annealing process module of claim 12, wherein the first predetermined range is plus or minus 10 percent from a respective target value.

18. The system of claim 15, wherein the at least one implanter tool processes one wafer at a time.

19. The system of claim 11, wherein the at least one implant or annealing processing tool includes at least one annealing tool for at least reducing deviation in gate delay.

20. The system of claim 19, wherein the annealing tool is controlled by parameters that include at least one of a Rapid Thermal Processing (RTP) peak temperature level and anneal time length.

21. A system of processing a plurality of wafers for manufacturing semiconductor devices, comprising:

means for forming at least one critical dimension on at least one device being fabricated on at least one of the plurality of wafers;

means for measuring the at least one critical dimension of the at least one device being fabricated on the at least one of the plurality of wafers after the at least one critical dimension has been formed, wherein the means for measuring the at least one critical dimension is in an implant-annealing process module and before the at least one of the plurality of wafers is processed by at least one implant or annealing processing tool of the implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

means for determining at least one control parameter value of the at least one implant or annealing processing tool based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an energy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level;

means for controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value;

means for measuring at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension;

means for determining whether the measured at least one post process dimension is within a first predetermined range; and

means for sending the at least one of the plurality of wafers to a next processing tool upon determining that the measured at least one post process dimension is within the first predetermined range.

22. The system of claim 21 further comprising:

means for adjusting the at least one implant or annealing processing tool of the implant-annealing process module upon determining that the measured at least one post process dimension is not within the first predetermined range.

23. The system of claim 21 further comprising:

means for adjusting at least one parameter value to re-process the at least one of the plurality of wafers when the measured at least one post process dimension is not within the first predetermined range.

24. The system of claim 21 wherein the means for measuring at least one critical dimension comprises:

means for measuring a length of a gate on the one of the plurality of wafers.

25. The system of claim 21, wherein the at least one implant or annealing processing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay.

26. The system of claim 25, wherein the at least one implanting tool is a beamline type implanting tool.

27. The system of claim 22, wherein the first predetermined range is plus or minus 10 percent from a respective target value.

28. The system of claim 25, wherein the at least one implanter tool processes one wafer at a time.

29. The system of claim 21, wherein the at least one implant or annealing processing tool includes at least one annealing tool for at least reducing deviation in gate delay.

30. The system of claim 29, wherein the annealing tool is controlled by parameters that include at least one of a Rapid Thermal Processing (RTP) peak temperature level and anneal time length.

31. A computer-readable medium including instructions being executed by one or more computers, the instructions instructing the one or more computers and at least one metrology tool of an implant-annealing process module and at least one implant or annealing processing tool of the implant-annealing process module for processing a plurality of wafers for manufacturing semiconductor devices, the instructions comprising implementation of the sequential steps of:

(a) measuring at least one critical dimension of at least one device fabricated on at least one of the plurality of wafers by one of the at least one metrology tool of the implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

(b) determining at least one control parameter value of the at least one implant or annealing processing tool based on the measured at least one critical dimensions wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an enemy and tilt level, a pocket implant dose level, and a channel and channel VT adjust implant dose level;

(c) controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value;

(d) measuring at least one post process dimensions of the at least one of the plurality of wafers by one of the at least one metrology tool of the implant-annealing process module, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension; and

(e) determining whether the measured at least one post process dimension is within a first predetermined range.

32. The medium of claim 31 further comprising instructions to implement the step of:

(f) adjusting the at least one implant or annealing processing tool of the step (c) upon determining that the measured at least one post process dimension is not within the first predetermined range.

33. The medium of claim 31 further comprising instructions to implement the steps of:

(f) sending the at least one of the plurality of wafers to a next processing tool upon determining that the measured at least one past process dimension is within the first predetermined range; and

(g) adjusting the step (c) to re-process the at least one of the plurality of wafers when the measured at least one post process dimension is not within the first predetermined range.

34. The medium of claim 31 wherein step (a) comprises the step of:

measuring a length of a gate on the one of the plurality of wafers.

35. The medium of claim 31, wherein the at least one implant or annealing processing tool includes at least one implanter tool for implanting ions into a junction of said at least one device for at least reducing deviation in gate delay.

36. The medium of claim 35, wherein the at least one implanting tool is a beamline type implanting tool.

37. The medium of claim 31, wherein, in step (e), the first predetermined range is plus or minus 10 percent from a respective target value.

38. The medium of claim 35, wherein the at least one implanter tool processes one wafer at a time.

39. The medium of claim 31, wherein the at least one implant or annealing processing tool includes at least one annealing tool for at least reducing deviation in gate delay.

40. The medium of claim 39, wherein the annealing tool is controlled by parameters that include at least one of a Rapid Thermal Processing (RTP) peak temperature level and anneal time length.

41. A method of processing a plurality of wafers for manufacturing semiconductor devices, sequentially comprising:

(a) measuring at least one critical dimension of at least one device fabricated on at least one of the plurality of wafers by one of the at least one metrology tool of an implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

(b) determining at least one control parameter value of at least one implant or annealing processing tool of the implant-annealing process module based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an enemy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level;

(c) controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value;

(d) measuring at least one post process dimension of the at least one of the plurality of wafers by one of the at least one metrology tool of the implant-annealing process module, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension;

(e) determining whether the measured at least one post process dimension is within a first predetermined range;

(f) sending the at least one of the plurality of wafers to a next processing tool upon determining that the measured at least one post process dimension is within the first predetermined range; and

(g) adjusting the at least one implant or annealing processing tool upon determining that the measured at least one post process dimension is not within the first predetermined range, to thereby reduce deviation in gate delay.

42. A method of processing a plurality of wafers for manufacturing semiconductor devices, sequentially comprising:

(a) measuring at least one critical dimension of at least one device fabricated on at least one of the plurality of wafers by one of the at least one metrology tool of an implant-annealing process module, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

(b) determining at least one control parameter value of at least one implant or annealing processing tool of the implant-annealing process module based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an enemy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level;

(c) controlling the at least one implant or annealing processing tool of the implant-annealing process module to process the at least one of the plurality of wafers based on the at least one control parameter value;

(d) measuring at least one post process dimension of the at least one of the plurality of wafers by one of the at least one metrology tool of the implant-annealing process module, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension;

(e) determining whether the measured at least one post process dimension is within a first predetermined range; and

(f) re-processing the at least one of the plurality of wafers when the measured at least one post process dimension is not within the first predetermined range, to thereby reduce deviation in gate delay.

43. A semiconductor wafer processing system comprising:

a first metrology tool, of an implant-annealing process module, configured to measure at least one critical dimension of at least one device fabricated on at least one of a plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

a module controller configured to determine at least one control parameter value based on the measured at least one critical dimension, wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an energy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level;

at least one implant or annealing processing tool, of the implant-annealing process module, configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one control parameter value; and

a second metrology tool, of the implant-annealing process module, configured to measure at least one post process dimension of the at least one of the plurality of wafers, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension;

wherein the module controller is further configured to determine whether the measured at least one post process dimension is within a first predetermined range, configured to cause the at least one of the plurality of wafers to be sent to a next processing tool upon determining that the measured at least one post process dimension is within the first predetermined range, and configured to adjust the at least one implant or annealing processing tool, of the implant-annealing process module, upon determining that the measured at least one post process dimension is not within the first predetermined range, to thereby reduce deviation in gate delay.

44. A semiconductor wafer processing system comprising:

a first metrology tool, of an implant-annealing process module, configured to measure at least one critical dimension of at least one device fabricated on at least one of a plurality of wafers, wherein a variation in the at least one critical dimension causes a variation in performance of the at least one device;

a module controller configured to determine at least one control parameter value based on the measured at least one critical dimension wherein the at least one control parameter value is selected from the group that consists of a halo angle, a Source Drain-Extension (SDE) dose level, an energy and tilt level, a pocket implant dose level, and a channel and channel V_T adjust implant dose level; and

a first implant or annealing processing tool, of an implant-annealing process module, configured to be controlled by the module controller in processing the at least one of the plurality of wafers based on the at least one control parameter value, wherein the module controller is further configured to collect measurement of at least one post process dimension of the at least one of a plurality of wafers, wherein the at least one post process dimension is junction depth and is different from the at least one critical dimension, configured to determine whether or not the measured at least one post process dimension is within a first predetermined range, and configured to adjust the at least one parameter value to re-process the one of at least one of the plurality of wafers when the measured at least one post process dimension is not within the first predetermined range to thereby reduce deviation in gate delay.