Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms

• US 7,225,281 B2
• Filed: 08/05/2002
• Issued: 05/29/2007
• Est. Priority Date: 08/27/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Rosenbluth, Mark B., Wolrich, Gilbert, Adiletta, Matthew J., Wilde, Myles J.
• Primary Examiner(s): Myers; Paul R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US10/212,944
• Publication Number:
  US 20030105899A1
• Time in Patent Office: 1,758 Days
• Field of Search: 710104-107, 710110-125, 710309-317, 710240-244, 710/31, 712 28- 31
• US Class Current: 710/104
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4004 Coupling between buses

Abstract

A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.

Claims

1. A method comprising:

transferring a command including a target identification between one or more bus masters and bus targets over a multiprocessor bus structure, the command including information that is interpreted differently by one of the bus targets based on the target identification.

2. The method of claim 1 wherein the target identification is a field in the command.

3. The method of claim 1 wherein the bus structure includes a separate command bus, push bus and pull bus.

4. The method of claim 1 wherein transferring includes sending the command to all of the bus targets over the command bus so that each bus target can determine if the command is intended for such target.

5. The method of claim 1 wherein the command is formatted to specify one of a plurality of operation types, and the command includes at least one field that is interpreted according to the which one of the plurality of operation types is specified in the command.

6. The method of claim 2 wherein at least one of the units acts as one of the bus masters at times and acts as one of the bus targets at other times.

7. The method of claim 3 wherein the bus structure further includes arbiters, the arbiters including a command arbiter associated with the command bus, a push arbiter associated with the push bus and a pull arbiter associated with the pull bus.

8. The method of claim 3, wherein the bus target identified in the command controls the transfer of information over the push bus to one of the bus masters for a push operation.

9. The method of claim 3 wherein the bus target identified in the command is operable to control transfer of information over the pull bus from one of the master buses to the bus target for a pull operation.

10. The method of claim 9 wherein the one of the bus masters is identified in the command by an identifier in a source field in the command.

11. The method of claim 8 wherein the one of the bus masters is identified in the command by an identifier in a destination field in the command.

12. The method of claim 7 wherein the bus masters arbitrate for use of the command using the command arbiter, and the bus targets arbitrate for use of the push and pull buses using the respective push and pull arbiters.

13. An article comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

transferring a command over a multiprocessor bus to bus targets, the command being formatted to identify one of the bus targets and include information that is interpreted differently based on which one of the bus targets is identified.

14. The article of claim 13 wherein the bus structure includes a separate command bus, push bus and pull bus.

15. An apparatus comprising:

a plurality of units;

a multiprocessor bus structure to enable communication exchanges between the units connected to the bus structure, with one or more of the units being bus masters and others of the units being bus targets, the bus masters operable to send a command to bus targets over the bus structure, the command formatted to identify one of the bus targets and having information that is interpreted differently based on which one of the bus targets is identified.

16. The apparatus of claim 15 wherein the bus structure includes a separate command bus, push bus and pull bus.

17. The apparatus of claim 15 wherein the command is formatted to specify one of a plurality of operation types, and the command includes at least one field that is interpreted according to the which one of the plurality of operation types is specified in the command.

18. The apparatus of claim 16, wherein the command is sent to all of the bus targets over the command bus to all of the bus targets and each bus target determines if the command is intended for such target.

19. The apparatus of claim 16, wherein the bus target identified in the command is operable to control transfer of information over the push bus to one of the bus masters for a push operation.

20. The apparatus of claim 16, wherein the bus target identified in the command is operable to control transfer of information over the pull bus from one of the bus masters to the bus target for a pull operation.

21. The apparatus of claim 19, wherein the one of the bus masters is identified in the command by an identifier in a destination field in the command.

22. The apparatus of claim 20, wherein the one of the bus masters is identified in the command by an identifier in a source field in the command.

23. An apparatus comprising:

a bus master operable to send a command to bus targets over a multiprocessor bus structure, the command being formatted to identify one of the bus targets and including information that is interpreted differently based on which one of the bus targets is identified.

24. The apparatus of claim 23 wherein the command is formatted to specify one of a plurality of operation types, and the command includes at least one field that is interpreted according to the which one of the plurality of operation types is specified in the command.

25. An apparatus comprising:

a bus target operable to receive a command from a bus master over a multiprocessor bus structure, the command being formatted to identify the bus target that receives the command; and

logic in the bus target to interpret information that is received by the bus target identified in the command, wherein the logic in the bus target interprets the information differently than corresponding logic in different bus target connected to the bus structure.

26. The apparatus of claim 25 wherein logic processes the command that is formatted to specify one of a plurality of operation types, and the command includes at least one field interpreted according to the which one of the plurality of operation types is specified in the command.