Increasing the quantity of I/O decode ranges using SMI traps

• US 7,225,284 B2
• Filed: 08/02/2004
• Issued: 05/29/2007
• Est. Priority Date: 08/02/2004
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Gupta, Saurabh, Rangarajan, Madhusudhan
• Primary Examiner(s): Myers; Paul R.
• Assistant Examiner(s): MISIURA, BRIAN THOMAS
• Application Number:
  US10/909,657
• Publication Number:
  US 20060026321A1
• Time in Patent Office: 1,030 Days
• Field of Search: None
• US Class Current: 710/266
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset including generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap. The I/O address operably received at the chipset via a bus. The method further including automatically reprogramming a decode register in the chipset such that the I/O address forwards the information to a device on the bus.

Claims

1. A method of increasing the quantity of input/output (I/O) decode ranges in a chipset, comprising:

generating a system management interrupt (SMI) based on information causing access to an I/O address that triggers a SMI trap, the I/O address operably received at the chipset via a bus;

automatically reprogramming a decode register in the chipset to include the I/O address such that the chipset forwards the information to a device on the bus;

automatically entering a SMI handler based on the generation of the SMI;

upon entry into the SMI handler, deactivating the SMI trap and resending information that accesses the I/O address to allow the information to be forwarded to the device on the bus; and

following the resend, re-activating the SMI trap.

2. The method of claim 1, further comprising programming a SMI trap in basic I/O system (BIOS) during an initialization process.

3. The method of claim 2, wherein the initialization process comprises a power on self test (POST) operation.

4. The method of claim 1, further comprising storing a current value of the decode register.

5. The method of claim 4, further comprising restoring the current value of the decode register after resending the information.

6. The method of claim 1, further comprising storing the I/O addresses that trigger a SMI trap in memory.

7. The method of claim 6, wherein reprogramming the decode register further comprises reprogramming the decode register to cycle through each decode register and I/O address stored in memory to send the information in a broadcast fashion along the bus.

8. The method of claim 1, further comprising positively decoding the I/O address.

9. An information handling system, comprising:

a processor;

a memory coupled to the processor;

a chipset communicatively coupled to the processor and the memory such that the chipset operably receives input/output (I/O) address from the processor via a bus;

the chipset including a decode register having at least one decode range, the decode range operable to route information to a computer device associated with the decode range;

a stored decode register communicatively coupled to the chipset, the stored decode register operably stores an I/O address;

a system management interrupt (SMI) trap operably set to generate a SMI, whereby during the SMI, a SMI handler reprograms the decode register to include at least one of the I/O addresses to allow the information to be forwarded to the respective computer device on the bus; and

a system basic I/O system (BIOS) handler operable to cause the I/O address to be resent such that the I/O address is forwarded to the device on the bus.

10. The information handling system of claim 9, wherein the SMI trap comprises a trap set programmed in a Basic I/O system (BIOS).

11. The information handling system of claim 9, wherein the chipset comprises an I/O controller hub.

12. The information handling system of claim 9, wherein the bus is a low pin count bus.

13. A tangible computer-readable medium having computer-executable instructions for performing a method of increasing the quantity of input/output (I/O) decode ranges, comprising:

programming a system management interrupt (SMI) trap in a basic I/O system (BIOS) to generate a SMI, the SMI trap operably triggered from information accessing an I/O address;

upon generation of the SMI, saving a current value of a decode range register in memory and deactivating the SMI trap;

automatically reprogramming a decode range register to include the I/O address;

following the reprogramming of the decode range register, resending the information accessing the I/O address and restoring the decode range register to the current value; and

re-activating the SMI trap.

14. The tangible computer-readable medium of claim 13, further comprising scanning an information handling system to determine the number of computer devices placed on a bus.

15. The tangible computer-readable medium of claim 14, further comprising, based on the scan, storing I/O addresses for the computer devices in memory.

16. The tangible computer-readable medium of claim 15, further comprising performing a debugging operation.

17. The tangible computer-readable medium of claim 16, wherein the debugging operation further comprises:

repeating the programming of the decode range register for each I/O address stored in memory; and

resending the information for each of the I/O addresses to allow the information to be sent to each device on the bus in a broadcast fashion.