Memory module with termination component

• US 7,225,292 B2
• Filed: 09/01/2005
• Issued: 05/29/2007
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US11/219,096
• Publication Number:
  US 20060039174A1
• Time in Patent Office: 635 Days
• Field of Search: None
• US Class Current: 711/105
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.

Claims

1. A memory module comprising:

a plurality of memory devices;

a termination component;

a control signal path coupled to each memory device of the plurality of memory devices, and the termination component, the control signal path extending along the plurality of memory devices such that signals propagating on the control signal path propagate past each of the memory devices of the plurality of memory devices in succession before reaching the termination component; and

a plurality of data signal paths, wherein a unique set of data signal paths of the plurality of data signal paths is coupled to each memory device of the plurality of memory devices, and wherein the unique set of data signal paths includes a first plurality of data signal conductors to convey a data value and at least one mask signal conductor to convey a write mask signal that indicates whether the data value is to be stored within the memory device to which the unique set of data signal paths is coupled.

2. The memory module of claim 1, further comprising a plurality of termination components, wherein each termination component of the plurality of termination components is disposed on a memory device of the plurality of memory devices and wherein each termination component of the plurality of termination components is coupled respectively to the unique set of data signal paths corresponding to each memory device of the plurality of memory devices.

3. The memory module of claim 1, wherein the control signal path includes signal lines to provide address information to the plurality of memory devices.

4. The memory module of claim 3, wherein the control signal path includes signal lines to provide control information to the plurality of memory devices.

5. The memory module of claim 1, wherein each memory device of the plurality of memory devices comprises receive circuitry to receive address information via the control signal path and control information via the control signal path.

6. The memory module of claim 1, further comprising a timing signal path to convey a timing signal that indicates a time at which signals transmitted on the control signal path are to be sampled by the plurality of memory devices.

7. The memory module of claim 6, wherein the timing signal is a strobe signal.

8. The memory module of claim 6, wherein the timing signal path extends alongside the control signal path such that the timing signal propagates past each memory device of the plurality memory devices in the same succession as signals propagating on the control signal path.

9. The memory module of claim 1, further comprising a plurality of timing signal paths that correspond respectively to the plurality of data signal paths, each timing signal path of the plurality of timing signal paths to convey a respective timing signal that indicates a time at which write data signals transmitted on the corresponding data signal path are to be sampled by a respective memory device of the plurality of memory devices.

10. A memory system comprising:

a memory controller;

a memory module having a row of memory devices and a termination component, each memory device in the row having a dedicated data signal path coupled to the memory controller, wherein each dedicated data signal path includes a first plurality of data signal conductors to convey a data value and at least one mask signal conductor to convey a write mask signal that indicates whether the data value is to be stored within the memory device to which the dedicated data signal path is coupled;

a control signal path coupled to each of the memory devices in the row and the termination component, the control signal path extending along the row of memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component.

11. The memory system of claim 10, further comprising a plurality of termination components, wherein each termination component of the plurality of termination components is disposed on a memory device of the row and wherein each termination component of the plurality of termination components is coupled respectively to the dedicated data signal path of each memory device in the row.

12. The memory system of claim 10, wherein the control signal path includes signal lines to provide address information to each of the memory devices in the row.

13. The memory system of claim 12, wherein the control signal path includes signal lines to provide control information to each of the memory devices in the row.

14. The memory system of claim 10, wherein each of the memory devices in the row comprises receive circuitry to receive address information via the control signal path and control information via the control signal path.

15. The memory system of claim 10, further comprising a timing signal path to convey a timing signal that indicates a time at which signals transmitted on the control signal path are to be sampled by each of the memory devices in the row.

16. The memory system of claim 15, wherein the timing signal is a strobe signal.

17. The memory system of claim 15, wherein the timing signal path extends alongside the control signal path such that the timing signal propagates past each of the memory devices in the same succession as signals propagating on the control signal path.

18. The memory system of claim 10 further comprising a plurality of timing signal paths that correspond respectively to the dedicated data signal path of each of the memory devices in the row, each timing signal path of the plurality of timing signal paths to convey a respective timing signal that indicates a time at which write data signals transmitted on the corresponding dedicated data signal path are to be sampled by a respective memory device in the row.

19. The memory system of claim 10, wherein the memory controller comprises timing circuitry to delay transmission of data signals on the dedicated data signal path of each of the memory devices in the row by a respective time interval that is based, at least in part, on a time required for a control signal to propagate on the control signal path from the memory controller to a corresponding memory device in the row.

20. A memory system comprising:

a memory controller;

a first memory module having a first plurality of memory devices and a first termination component, each memory device of the first plurality of memory devices having a separate data signal path that is coupled to the memory controller, wherein each separate data signal path includes a first plurality of data signal conductors to convey a data value and at least one mask signal conductor to convey a write mask signal that indicates whether the data value is to be stored within the memory device to which the separate data signal path is coupled;

a first control signal path coupled to the first plurality of memory devices and the first termination component, the first control signal path extending along the first plurality of memory devices such that signals propagating on the first control signal path propagate past each memory device of the first plurality of memory devices in sequence before reaching the first termination component; and

a second memory module having a second plurality of memory devices and a second termination component, each memory device of the second plurality of memory devices having a separate data signal path that is coupled to the memory controller; and

a second control signal path coupled to the second plurality of memory devices and the second termination component, the second control signal path extending along the second plurality of memory devices such that signals propagating on the second control signal path propagate past each memory devices of the second plurality of memory devices in sequence before reaching the second termination component.

21. A memory module comprising:

a plurality of memory devices;

a termination component;

a signal path coupled to each memory device of the plurality of memory devices and the termination component, the signal path extending along the plurality of memory devices such that signals propagating on the signal path propagate past each of the memory devices before reaching the first termination component;

a plurality of data signal paths, wherein each data signal path of the plurality of data signal paths is coupled to a respective memory device of the plurality of memory device, and wherein each data signal path includes a first plurality of data signal conductors to convey a data value and at least one mask signal conductor to convey a write mask signal that indicates whether the data value is to be stored within the respective memory device to which the data signal path is coupled;

a plurality of termination components, wherein each termination component of the plurality of termination components is disposed on a memory device of the plurality of memory devices and wherein each termination component of the plurality of termination components is coupled respectively to a respective data signal path of the plurality of data signal paths; and

a plurality of timing signal paths, each timing signal path of the plurality of timing signal paths to convey a respective timing signal that indicates a time at which write data signals transmitted on the corresponding data signal path of the plurality of data signal paths is to be sampled by a respective memory device of the plurality of memory devices.

22. A memory module comprising:

a plurality of memory devices;

a termination component;

an address signal path coupled to each memory device of the plurality of memory devices and the termination component, the address signal path extending along the plurality of memory devices such that address signals propagating on the address signal path propagate past each of the memory devices in order before reaching the termination component; and

a plurality of data signal paths, wherein a unique set of data signal paths of the plurality of data signal paths is coupled to each memory device of the plurality of memory devices, and wherein the unique set of data signal paths includes a first plurality of data signal conductors to convey a data value and at least one mask signal conductor to convey a write mask signal that indicates whether the data value is to be stored within the memory device to which the unique set of data signal paths is coupled.