External memory controller node
First Claim
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1. A memory controller for an adaptable computing circuit, the adaptable computing circuit having a programmable network and couplable to a memory, the controller comprising:
- a network interface configured to receive a memory request from the programmable network and to send data to and receive data from the programmable network;
a memory interface configured to access a memory to fulfill the memory request; and
at least one memory processing circuit coupled to the network interface and to the memory interface, the memory processing circuit configured to provide a memory access service of a plurality of memory access services,wherein the memory interface receives and provides data for the memory request using the memory access service.
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Abstract
A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
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Citations
28 Claims
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1. A memory controller for an adaptable computing circuit, the adaptable computing circuit having a programmable network and couplable to a memory, the controller comprising:
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a network interface configured to receive a memory request from the programmable network and to send data to and receive data from the programmable network; a memory interface configured to access a memory to fulfill the memory request; and at least one memory processing circuit coupled to the network interface and to the memory interface, the memory processing circuit configured to provide a memory access service of a plurality of memory access services, wherein the memory interface receives and provides data for the memory request using the memory access service. - View Dependent Claims (2, 3, 4)
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5. A memory controller for an adaptable computing circuit, the adaptable computing circuit having an interconnection network coupled to a plurality of nodes, the controller comprising:
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a network interface configured to receive a memory request for a memory access service from the interconnection network; and a memory processing circuit configured to receive the memory request and to provide a memory access service of a plurality of memory access services, the memory access service associated with the memory request, and wherein the plurality of memory access services comprise at least one of a retrieve/write (“
peek/noke”
) service, a memory random access service, a point-to-point service, a direct memory access service, a messaging service and a real-time input service. - View Dependent Claims (6, 7)
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8. A memory controller in an adaptable computing circuit, the controller comprising:
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one or more ports configured to receive memory requests, wherein each port includes one or more parameters; a memory processing circuit configured to receive a memory request from a port in the one or more ports; and a data address generator configured to generate a memory location for a memory based on the one or more parameters associated with the port, wherein the memory processing circuit is further configured to perform a memory operation for the memory request using the generated memory location, the memory processing circuit comprising a processing circuit to perform at least one of point-to-point memory requests, direct memory access memory requests, and real-time input memory requests. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory controller in an adaptable computing circuit the controller comprising:
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one or more ports configured to receive memory requests from requesting nodes, wherein each port includes one or more parameters, the one or more parameters configurable by information in the memory requests; a data address generator configured to generate a memory location for a memory based on the one or more parameters associated with the port; and a point-to-point engine configured to receive a memory request from a port in the one or more ports and to perform a memory operation using the generated memory location while adhering to a point-to-point protocol with the requesting node. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A system for processing memory service requests in an adaptable computing environment, the system comprising:
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a memory; one or more nodes configured to generate a memory service request; a memory controller configured to receive the memory service request, the memory controller configured to service the memory service request by reading data from or writing data to the memory based on the memory service request, and the memory controller further configured to provide at least one of a retrieve/write (“
peek/poke”
) service, a memory random access service, a point-to-point service, a direct memory access service, a messaging service and a real-time input service. - View Dependent Claims (25, 26, 27, 28)
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Specification