Method and apparatus for accessing a dynamic memory device by providing at least one of burst and latency information over at least one of redundant row and column address lines

• US 7,225,303 B2
• Filed: 09/22/2003
• Issued: 05/29/2007
• Est. Priority Date: 09/22/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Choi, Joo S.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US10/668,009
• Publication Number:
  US 20050066141A1
• Time in Patent Office: 1,345 Days
• Field of Search: 711/168, 711/170, 711/104, 711/105, 711/154, 365/230.01, 365/233, 365/189.01
• US Class Current: 711/154
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A method and apparatus are provided for accessing a dynamic memory device. The method comprises receiving a command from a controller to access a memory, receiving, from the controller, at least one of burst length information and latency information in association with the command to access the memory; and providing data to or from the memory in response to the command based on at least one of the burst length information and the latency information.

Claims

1. A method, comprising:

receiving a command from a controller to access a memory in response to a memory request received from a source;

determining the desired burst length information or latency information in response to receiving the memory request from the source; and

providing data to or from the memory based on at least one of the burst length information and the latency information in response to receiving the burst length information or latency information over at least one of a redundant row address line and a redundant column address line.

2. The method of claim 1, wherein receiving a command comprises receiving at least one of a READ operation and WRITE operation to access the contents of the memory.

3. The method of claim 2, wherein determining the latency information comprises receiving at least one of column address strobe latency information and write latency information.

4. The method of claim 1, wherein determining the desired burst length information comprises determining the desired burst length information based on an amount of data to be retrieved from the memory.

5. The method of claim 1, wherein determining the burst length information comprises determining the burst length information based on the source that provides the memory request.

6. An apparatus, comprising:

a controller adapted to;

provide a command to access a memory array in response to a memory request received from a source;

determine at least one of burst length information and latency information;

provide the at least one of burst length information and latency information over at least one of a redundant row address line and a redundant column address line; and

receive data from the memory array based on at least one of the burst length information and the latency information.

7. The apparatus of claim 6, wherein the controller is adapted to issue a READ operation access the contents of the memory.

8. The apparatus of claim 6, wherein the controller is adapted to provide at least one of the burst length information and the latency information contemporaneously with the command to access the memory.

9. The apparatus of claim 6, wherein the controller is adapted to provide a burst length of a first pre-selected value in response to receiving a request from a peripheral client and a burst length of a second pre-selected value in response to receiving a request from a main client, wherein the first pre-selected value is less than the second pre-selected value.

10. The apparatus of claim 6, wherein the controller is adapted to issue a WRITE command and adapted to provide write latency information contemporaneously with the WRITE command.

11. A system, comprising:

a memory array, and

a controller communicatively coupled to the memory array, the controller adapted to;

provide a command to access the memory array in response to a memory request received from a source; and

determine at least one of burst length information and latency information in response to receiving the memory request;

provide the at least one of burst length information and latency information over least one of a redundant row address line and a redundant column address line; and

wherein the memory array is adapted to provide or receive data based on at least one of the burst length information and the latency information.

12. The system of claim 11, wherein the controller is adapted to issue at least one of a READ operation and WRITE operation access the contents of the memory.

13. The system of claim 11, wherein the controller is adapted to provide at least one of the burst length information and the latency information contemporaneously with the command to access the memory.

14. The system of claim 11, wherein the controller is adapted to provide a burst length of a first pre-selected value in response to receiving a request from a peripheral client and a burst length of a second pre-selected value in response to receiving a request from a main client, wherein the first pre-selected value is less than the second pre-selected value.

15. An apparatus, comprising:

means for providing a command from a controller to access a memory in response to a memory request received from a source;

means for determining burst length information or latency information in response to receiving the memory request;

means for providing the at least one of burst length information and latency information over a redundant address line, wherein the redundant address line comprises at least one of a redundant row address line and a redundant column address line; and

means for providing data to or from the memory based on at least one of the burst length information and the latency information.

16. An apparatus, comprising:

a memory adapted to;

receive a request to access contents of the memory;

receive, from the memory controller, at least one of burst length information and latency information over at least one of a redundant row address line and a redundant column address line; and

provide data from the memory based on at least one of the burst length information and the latency information.

17. The apparatus of claim 16, wherein memory is adapted to receive at least one of the burst length information and the latency information contemporaneously with the command to access the memory.

18. The apparatus of claim 16, wherein the memory is adapted to receive a burst length of a first pre-selected value in response to the controller receiving a request from a peripheral client and a burst length of a second pre-selected value in response to the controller receiving a request from a main client, wherein the first pre-selected value is less than the second pre-selected value.

19. The apparatus of claim 16, wherein the memory is adapted to receive a WRITE command and adapted to receive write latency information contemporaneously with the WRITE command.