ABIST-assisted detection of scan chain defects

• US 7,225,374 B2
• Filed: 12/04/2003
• Issued: 05/29/2007
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Forlenza, Orazio Pasquale, Forlenza, Donato Orazio, Burdine, Todd Michael, Hurley, William James, Michnowski, Steven, Webb, James Bernard
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US10/728,348
• Publication Number:
  US 20050138514A1
• Time in Patent Office: 1,272 Days
• Field of Search: 714/724, 714726-729, 716/4
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits

Abstract

An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.

Claims

1. A method of detecting a defect in a scan chain, the method comprising:

applying a plurality of pattern sets to a scan chain using an array built-in self-test (ABIST) circuit coupled to the scan chain;

collecting, from the scan chain, scan out data generated as a result of the application of the plurality of pattern sets to the scan chain; and

using the collected scan out data to identify a defective latch in the scan chain.

2. The method of claim 1, further comprising:

sensitizing at least one alternate path within which the scan chain is disposed; and

applying a second plurality of pattern sets to the scan chain while the alternate path is sensitized.

3. The method of claim 1, wherein using the collected scan out data to identify the defective latch includes identifying a location of the defective latch in the scan chain.

4. The method of claim 1, further comprising performing at least one of a scan test and a flush test prior to applying the plurality of pattern sets to the scan chain.

5. The method of claim 1, wherein applying the plurality of pattern sets includes laterally inserting each pattern set into the scan chain using the ABIST circuit.

6. The method of claim 1, wherein collecting the scan out data includes serially stepping the scan out data through the scan chain to an output thereof.

7. The method of claim 1, further comprising reconfiguring the scan chain prior to collecting the scan out data.

8. An apparatus, comprising:

a memory; and

program code resident in the memory and configured to detect a defect in a scan chain disposed in an integrated circuit device by collecting, from the scan chain, scan out data generated as a result of an application of a plurality of pattern sets to the scan chain by an array built-in self-test (ABIST) circuit disposed in the integrated circuit device, and using the collected scan out data to identify a defective latch in the scan chain.

9. The apparatus of claim 8, wherein the program code is further configured to sensitize at least one alternate path within which the scan chain is disposed, and apply a second plurality of pattern sets to the scan chain while the alternate path is sensitized.

10. The apparatus of claim 8, wherein the program code is configured to use the collected scan out data to identify the defective latch by identifying a location of the defective latch in the scan chain.

11. The apparatus of claim 8, wherein the program code is further configured to perform at least one of a scan test and a flush test prior to applying the plurality of pattern sets to the scan chain.

12. The apparatus of claim 8, wherein the program code is configured to apply the plurality of pattern sets by laterally inserting each pattern set into the scan chain using the ABIST circuit.

13. The apparatus of claim 8, wherein the program code is configured to collect the scan out data by serially stepping the scan out data through the scan chain to an output thereof.

14. The apparatus of claim 8, wherein the program code is further configured to reconfigure the scan chain prior to collecting the scan out data.

15. The apparatus of claim 8, wherein at least a portion of the program code is resident in a test platform.

16. The apparatus of claim 15, wherein at least a second portion of the program code is resident in computer coupled to the test platform.

17. A program product, comprising:

program code configured to detect a defect in a scan chain disposed in an integrated circuit device by collecting, from the scan chain, scan out data generated as a result of an application of a plurality of pattern sets to the scan chain by an array built-in self-test (ABIST) circuit disposed in the integrated circuit device, and using the collected scan out data to identify a defective latch in the scan chain; and

a computer readable signal bearing medium bearing the program code.

18. The program product of claim 17, wherein the computer readable signal bearing medium includes at least one of a transmission medium and a recordable medium.

19. A method of detecting a defect in a scan chain, the method comprising:

applying a first plurality of pattern sets to a scan chain coupled to an array built-in self-test (ABIST) circuit;

collecting, from the scan chain, scan out data generated as a result of the application of the first plurality of pattern sets to the scan chain;

using the collected scan out data to identify a defective latch in the scan chain;

sensitizing at least one alternate path within which the scan chain is disposed; and

applying a second plurality of pattern sets to the scan chain while the alternate path is sensitized.

20. An apparatus, comprising:

a memory; and

program code resident in the memory and configured to detect a defect in a scan chain disposed in an integrated circuit device by collecting, from the scan chain, scan out data generated as a result of an application of a first plurality of pattern sets to the scan chain by an array built-in self-test (ABIST) circuit disposed in the integrated circuit device, and using the collected scan out data to identify a defective latch in the scan chain, wherein the program code is further configured to sensitize at least one alternate path within which the scan chain is disposed, and apply a second plurality of pattern sets to the scan chain while the alternate path is sensitized.