MEMS device wafer-level package

• US 7,226,810 B2
• Filed: 06/20/2005
• Issued: 06/05/2007
• Est. Priority Date: 04/29/2002
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Knipe, Richard L., Kocian, Thomas A., Strumpell, Mark H.
• Primary Examiner(s): Geyer; Scott B.
• Application Number:
  US11/157,024
• Publication Number:
  US 20050233498A1
• Time in Patent Office: 715 Days
• Field of Search: 438/14, 438/15, 438/17, 438/106, 438/107, 438/110, 438/112, 438/113, 438/116, 438/118, 438/455, 438/456
• US Class Current: 438/110
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 99/004 during manufacturing
• CPC Class Codes: B81C 99/0065 Process control; Yield prediction
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

Claims

1. A method of manufacturing a semiconductor device comprising:

a) providing a semiconductor wafer;

b) forming a plurality of dies on the semiconductor wafer;

c) performing an inspection of the plurality of dies;

d) attaching windows to dies that pass the inspection and not attaching windows that do not pass the inspection, while the dies are still part of the wafer; and

e) cutting the semiconductor wafer into individual devices.

2. The method of claim 1 wherein the inspection is an electrical test.

3. The method of claim 1 wherein the inspection is a visual inspection.

4. The method of claim 1 wherein at least one die comprises an optical device.

5. The method of claim 4 wherein the optical device is a digital micromirror device.

6. The method of claim 1 and further comprising the step of performing one or more additional inspections after the attaching step and prior to said cutting step.

7. The method of claim 6 wherein at least one of the additional inspections includes operational testing.

8. The method of claim 7 wherein the operational testing includes projecting an image from at least one of the dies.

9. The method of claim 6 where at least some of the inspections are performed outside of the wafer fabrication area.