Charge trapping memory cell and fabrication method

• US 7,227,219 B2
• Filed: 02/10/2005
• Issued: 06/05/2007
• Est. Priority Date: 02/10/2004
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Mikolajick, Thomas
• Primary Examiner(s): Andujar; Leonardo
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US11/055,584
• Publication Number:
  US 20050189582A1
• Time in Patent Office: 845 Days
• Field of Search: None
• US Class Current: 257/324
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.

Claims

1. A charge trapping memory cell comprising:

a well in a semiconductor body, said well being doped to a first conductivity type,

a source region and a drain region formed at a top side of the semiconductor body and doped to a second conductivity type tat is opposite the first conductivity type;

a trench formed in the semiconductor body, said trench extending into the doped well below the source and drain regions;

a first gate electrode located at least in a bottom portion of the trench, said first gate electrode electrically insulated from the well by a gate dielectric;

a second gate electrode extending into the trench toward said first gate electrode and arranged in the trench above the first gate electrode and electrically insulated from the first gate electrode; and

a storage layer sequence comprising first and second boundary layers and a storage layer, said storage layer provided for charge trapping being sandwiched between said first and second boundary layers, and at least portions of the storage layer sequence being arranged between the second gate electrode and the doped well and/or between the second gate electrode and the source and drain regions.

2. The charge trapping memory cell of claim 1 and further comprising:

a word line coupled to the second gate electrode;

source/drain lines coupled to the source and drain regions; and

a control gate coupled to the first gate electrode.

3. The charge trapping memory cell as claimed in claim 1, wherein the first gate electrode and the second gate electrode are insulated from one another by a portion of the storage layer sequence.

4. The charge trapping memory cell as claimed in claim 1, wherein a portion of the storage layer sequence reaches as far as an upper edge of the first gate electrode.

5. The charge trapping memory cell of claim 1, wherein the storage layer sequence comprises a nitride layer sandwiched between first and second oxide layers.

6. The charge trapping memory cell of claim 1, wherein the gate electrode comprises polysilicon.

7. The charge trapping memory cell of claim 1, wherein the semiconductor body comprises a semiconductor substrate.

8. The charge trapping memory cell of claim 1, wherein portions of the storage layer sequence are arranged between the second gate electrode and the doped well.

9. The charge trapping memory cell of claim 8, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.

10. The charge trapping memory cell of claim 1, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.

11. A charge trapping memory cell comprising:

a well in a semiconductor body, said well being doped to a first conductivity type,

a source region and a drain region formed at a top side of the semiconductor body and doped to a second conductivity type that is opposite the first conductivity type;

a trench formed in the semiconductor body, said trench extending into the doped well below the source and drain regions;

a gate electrode, which is electrically insulated from the well by a gate dielectric, the gate electrode being arranged as a first gate electrode in the trench and at least in a bottom portion of the trench;

a second gate electrode arranged in the trench above the first gate electrode and electrically insulated from the first gate electrode; and

a storage layer sequence comprising first and second boundary layers and a storage layer, said storage layer provided for charge trapping being sandwiched between said first and second boundary layers, and at least portions of the storage layer sequence being arranged between the second gate electrode and the doped well and other portions being arranged between the second gate electrode and the source and drain regions.

12. A charge trapping memory cell comprising:

a well in a semi conductor body, said well being doped to a first conductivity type,

a source region and a drain region formed at a top side of the semiconductor body and doped to a second conductivity type that is opposite the first conductivity type;

a trench formed in the semiconductor body, said trench extending into the doped well below the source and drain regions;

a gate electrode, which is electrically insulated from the well by a gate dielectric, the gate electrode being arranged as a first gate electrode in the trench and at least in a bottom portion of the trench;

a second gate electrode arranged in the trench above the first gate electrode and electrically insulated from the first gate electrode; and

a storage layer sequence comprising first and second boundary layers and a storage layer, said storage layer provided for charge trapping being sandwiched between said first and second boundary layers, and at least a portion of the storage layer sequence providing said electrical insulation between said first gate electrode and said second electrode, and another portion being arranged between the second gate electrode and the doped well and/or between the second gate electrode and the source and drain regions.

13. The charge trapping memory cell of claim 12 and further comprising:

a word line coupled to the second gate electrode;

source/drain lines coupled to the source and drain regions; and

a control gate coupled to the first gate electrode.

14. The charge trapping memory cell as claimed in claim 12, wherein a portion of the storage layer sequence reaches as far as an upper edge of the first gate electrode.

15. The charge trapping memory cell of claim 12, wherein the storage layer sequence comprises a nitride layer sandwiched between first and second oxide layers.

16. The charge trapping memory cell of claim 12, wherein the gate electrode comprises polysilicon.

17. The charge trapping memory cell of claim 12, wherein the semiconductor body comprises a semiconductor substrate.

18. The charge trapping memory cell of claim 12, wherein portions of the storage layer sequence are arranged between the second gate electrode and the doped well.

19. The charge trapping memory cell of claim 18, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.

20. The charge trapping memory cell of claim 12, wherein portions of the storage layer sequence are arranged between the second gate electrode and the source and drain regions.