Low-K gate spacers by fluorine implantation

• US 7,227,230 B2
• Filed: 02/10/2004
• Issued: 06/05/2007
• Est. Priority Date: 01/15/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Tonti, William R., Mandelman, Jack
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US10/775,440
• Publication Number:
  US 20040171201A1
• Time in Patent Office: 1,211 Days
• Field of Search: 257/645, 257/651, 257/900, 257337-338, 257368-369
• US Class Current: 257/369
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

Claims

1. A MOSFET device comprising a silicon substrate having shallow trench isolation STI and source and drain regions located therein, a gate dielectric and a gate stack located on said silicon substrate between the source and drain regions, and a fluorine doped low K dielectric oxide gate spacer located on sidewalk of said gate stack, said fluorine doped low K dielectric oxide gate spacer having a fluorine content of about 1E14 to 2E16 cm⁻

2, wherein said fluorine doped low K dielectric oxide gate spacer is in direct contact with an overlying silicon nitride oxide layer and at least a portion of said source and drain regions directly contacts said silicon nitride oxide layer.

2. The MOSFET device of claim 1 wherein said fluorine doped low K dielectric oxide gate spacer has a dielectric constant value in a range of 3.3 to 4.0.

3. The MOSFET device of claim 1 wherein said fluorine doped low K dielectric oxide gate spacer has a dielectric constant value of substantially 3.3.

4. The MOSFET device of claim 1 wherein said silicon nitride oxide layer overlays said gate stack.

5. A MOSFET device comprising a silicon substrate having shallow trench isolation (STI) located therein, a gate dielectric and a gate stack located on said silicon substrate, a fluorine doped low K dielectric oxide gate spacer located on sidewalls of said gate stack, and a silicon nitride oxide layer overlaying and contacting said gate stack, said fluorine doped low K dielectric oxide gate spacer, and remaining surfaces of the silicon substrate, wherein no material with a dielectric constant greater than 4.0 is present between said fluorine doped low K dielectric oxide gate spacer and said silicon nitride oxide layer.