Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM

• US 7,227,233 B2
• Filed: 09/12/2005
• Issued: 06/05/2007
• Est. Priority Date: 09/12/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Koburger, Charles W. III, Hakey, Mark C., Furukawa, Toshiharu, Horak, David V., Holmes, Steven J., Mandelman, Jack A.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US11/162,472
• Publication Number:
  US 20070057323A1
• Time in Patent Office: 631 Days
• Field of Search: 257/390, 257/E27.102, 257/E21.662, 257/E21.671
• US Class Current: 257/390
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/27 ROM only

Abstract

A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Claims

1. A Read Only Memory (ROM) array comprising:

a plurality of semiconductor lines oriented in a first direction;

a strap along at least one edge of each semiconductor line;

a plurality of conductive lines in a second direction orthogonal to said first direction;

a plurality of diodes in said plurality of semiconductor lines, each located at the intersection of one of said plurality of conductive lines with one of said plurality of semiconductor lines; and

a plurality of contacts, each connected between one of said plurality of conductive lines and an underlying one of said plurality of diodes.

2. A ROM array as in claim 1, wherein said strap extends from said one edge under said each semiconductor line by at least half the width of said each semiconductor line.

3. A ROM array as in claim 1, wherein one said strap is disposed under opposite edges of said each semiconductor line.

4. A ROM array as in claim 1, wherein each said strap is a segmented strap, each strap segment extending under the entire width of said each semiconductor line.

5. A ROM array as in claim 1, wherein said strap comprises a material including tungsten.

6. A ROM array as in claim 5, wherein said strap material is tungsten silicide.

7. A ROM array as in claim 1, wherein each said intersection locates a ROM cell, the presence of a contact in any said ROM cell being a one and the absence being a zero.

8. A ROM array as in claim 1, wherein said plurality of semiconductor lines are silicon lines in a surface layer of a silicon-on-insulator chip, each doped at said strap such that said strap forms a resistive contact with said each semiconductor line.

9. A silicon-on-insulator (SOI) integrated circuit (IC) chip, said SOI IC including a Read Only Memory (ROM) comprising:

a plurality of silicon lines in a first direction in a silicon surface layer of an SOI chip;

a strap along at least one edge of each silicon line;

a plurality of conductive lines in a second direction orthogonal to said first direction, a ROM cell being located at each intersection of one of said plurality of conductive lines with one of said plurality of silicon lines;

a plurality of diodes in said plurality of lines, each located in a corresponding ROM cell; and

a plurality of contacts, each connected between one of said plurality of conductive lines and an underlying one of said plurality of diodes, wherein the presence of a contact in any said ROM cell is a first logic state and the absence being a second logic state.

10. A SOI IC as in claim 9, wherein said strap extends from said one edge under said each silicon line by at least half the width of said each silicon line.

11. A SOI IC as in claim 9, wherein one said strap is disposed under opposite edges of said each silicon line.

12. A SOI IC as in claim 9, wherein each said strap is a segmented strap, each strap segment extending under the entire width of said each silicon line.

13. A SOI IC as in claim 9, wherein said strap comprises a material including tungsten.

14. A SOI IC as in claim 9, wherein said strap material is tungsten silicide.

15. A SOI IC as in claim 9, wherein said plurality of silicon lines is at least 4 silicon lines and said plurality of conductive lines is at least 4 conductive lines, each doped at said strap such that said strap forms a resistive contact with said each semiconductor line.