Safety interlock and protection circuit for permanent magnet motor drive

• US 7,227,331 B2
• Filed: 02/13/2006
• Issued: 06/05/2007
• Est. Priority Date: 02/14/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Takahashi, Toshio, Galli, Giovanni
• Primary Examiner(s): Leykin; Rita
• Application Number:
  US11/352,719
• Publication Number:
  US 20060181239A1
• Time in Patent Office: 477 Days
• Field of Search: 318/808, 318/807, 318/806, 318/805, 363/35, 363/34, 363/51
• US Class Current: 318/808
• CPC Class Codes: D06F 34/10 Power supply arrangements, e.g. stand-by circuits
• CPC Class Codes: D06F 37/42 Safety arrangements, e.g. for stopping rotation of the receptacle upon opening of the casing door
• CPC Class Codes: H02P 25/024 controlled by supply frequency
• CPC Class Codes: H02P 29/0241 the fault being an overvoltage

Abstract

A circuit for protecting against controller failure wherein the controller provides control signals for controlling a DC to AC inverter fed by a DC bus and driving a permanent magnet motor, the circuit comprising a first circuit for monitoring the DC bus voltage and, in the event the DC bus voltage exceeds a first threshold due to a counter EMF generated by the motor, for producing a signal to the controller to provide a switch state to the inverter whereby the counter EMF is dissipated substantially in a motor circuit resistance of the permanent magnet motor as a result of a short circuit condition provided by the switch state of the inverter, thereby preventing the DC bus voltage of the inverter from exceeding the first threshold and causing the permanent magnet motor speed to be reduced.

Claims

1. A circuit for protecting against controller failure wherein the controller provides control signals for controlling a DC to AC inverter fed by a DC bus and driving a permanent magnet motor, the circuit comprising:

a first circuit for monitoring the DC bus voltage and, in the event the DC bus voltage exceeds a first threshold due to a counter EMF generated by the motor, for producing a signal to the controller to provide a switch state to the inverter whereby the counter EMF is dissipated substantially in a motor circuit resistance of the permanent magnet motor as a result of a short circuit condition provided by the switch state of the inverter, thereby preventing the DC bus voltage of the inverter from exceeding the first threshold and causing the permanent magnet motor speed to be reduced.

2. The circuit of claim 1, further wherein the first circuit issues an interlock signal which will keep an enclosure housing the permanent magnet motor or a device driven by the motor locked while the motor is spinning.

3. The circuit of claim 2, wherein the permanent magnet motor drives the drum of a washing machine and the safety interlock signal prevents a door providing access to a rotating drum driven by the permanent magnet motor from being opened.

4. The circuit of claim 2, wherein the first circuit comprises a first sensing circuit coupled to DC bus for monitoring the DC bus voltage, and a comparator for comparing the sensed voltage to a reference voltage and for producing a first signal to cause the controller to provide the switch state causing the short circuit condition.

5. The circuit of claim 4, wherein the interlock signal is generated from said first signal.

6. The circuit of claim 4, wherein the switch state comprises the zero vector.

7. The circuit of claim 6, wherein the zero vector is the switch state 111 or 000.

8. The circuit of claim 1, wherein when the DC bus voltage is reduced below a second threshold, the switch state producing the short circuit condition is removed.

9. The circuit of claim 8, wherein the second threshold is above a nominal DC bus voltage.

10. The circuit of claim 8, wherein, should the DC bus voltage again increase beyond the first threshold, the switch state producing the short circuit condition is again reinstated by said first circuit, as many times as necessary to reduce the motor speed to a base value.

11. The circuit of claim 2, further comprising a second circuit monitoring the counter EMF generated by the motor.

12. The circuit of claim 11, wherein the second circuit comprises a second sensing circuit for each phase of the permanent magnet motor, the second sensing circuits each providing an output to a voltage summing circuit for summing the outputs to provide a summed output which is provided to the input of a further comparator for comparing said summed output to a further threshold to determine when the speed of the motor is reduced to a stopped condition.

13. The circuit of claim 10, wherein said summed output is low pass filtered before being provided to said further comparator.

14. The circuit of claim 1, wherein the switch state comprises the 000 or 111 vector or a combination of said 000 and 111 vectors applied in discrete time periods.

15. The circuit of claim 4, wherein the first sensing circuit comprises a resistor divider.

16. The circuit of claim 12, wherein the second sensing circuits each comprise a resistor divider circuit.

17. The circuit of claim 12, wherein the voltage summing circuit comprises an operational amplifier circuit.

18. The circuit of claim 11, wherein the second circuit prevents the interlock signal from being removed until the motor speed is substantially zero.

19. The circuit of claim 2, wherein the first circuit provides a signal to a latch circuit for issuing said interlock signal.

20. The circuit of claim 1, wherein the permanent magnet motor comprises a three phase permanent magnet motor.

21. The circuit of claim 1, wherein the motor circuit resistance comprises a resistance of the stator of the motor.

22. The circuit of claim 19, wherein the first circuit generates a first signal provided to one input of said latch circuit and the second circuit generates a second signal provided to a second input of said latch circuit.

23. The circuit of claim 22, wherein the first signal sets said latch circuit to provide said interlock signal and the second circuit resets the latch circuit to remove the interlock signal.

24. The circuit of claim 1, wherein the motor is operated with field weakening.