Apparatus and method for bus signal termination compensation during detected quiet cycle

• US 7,227,377 B2
• Filed: 12/31/2004
• Issued: 06/05/2007
• Est. Priority Date: 12/31/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kurts, Tsvika, Wayner, Zelig, Bojan, Tommy
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/026,651
• Publication Number:
  US 20050151562A1
• Time in Patent Office: 886 Days
• Field of Search: 326 30- 34, 326/86, 326/90
• US Class Current: 326/30
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Claims

1. A method comprising:

(a) determining a value to match a termination circuit to a characteristic impedance of a bus signal line;

(b) tracking bus protocol events to determine when a bus, that includes the line and that is used by a bus agent in a power consumption mode of operation, is available for adjusting the termination circuit; and

(c) when the bus becomes available as determined in (b), adjusting the termination circuit according to the determined value.

2. The method of claim 1 further comprising repeating (a) through (c) every predetermined time interval while the bus is being used by the agent in the power consumption mode of operation.

3. The method of claim 2 wherein adjusting the termination circuit comprises turning a transistor of the termination circuit on or off to make a discrete change in one of slew rate and pull-up impedance for an I/O buffer of the bus line.

4. The method of claim 3 wherein a pull-up voltage of the bus line is about 1 Volt or less.

5. The method of claim 1 wherein the value is determined by a voltage divider technique involving a precision off-chip resistor.

6. An integrated circuit die, comprising:

a bus agent having a plurality of bus I/O buffers each with a discretely adjustable on-chip termination circuit and each being designed to operate with a bus line pull-up supply voltage of about 1 Volt or less; and

an on-chip termination update unit (TUU) coupled to the plurality of buffers to change a termination of each of the plurality of buffers while the bus agent is operating in a power consumption modes,

wherein the TUU is to determine when a time interval is available, during operation of the bus agent in the power consumption mode, during which the termination of the plurality of buffers can be changed in discrete steps, without forcing a bus idle condition and without hampering the receipt of bus data symbols by the plurality of I/O buffers.

7. The integrated circuit of claim 6 wherein the termination takes on any one of at least 128 values represented by at least seven bits.

8. The integrated circuit of claim 6 further comprising a compensation pad to which an off-chip precision resistor is to be connected, the TUU to determine a termination compensation value, using the precision resistor, according to which the termination of the plurality of buffers is changed.

9. An electronic system comprising:

a bus;

a chipset integrated circuit (IC) coupled to the bus as a priority bus agent;

a processor IC having a plurality of bus buffers coupled to the bus, each of the plurality of buffers having a discretely adjustable on-chip termination circuit and designed to receive a supply voltage of about 1 Volt or less; and

a termination update unit (TUU) to change a termination of each of the plurality of buffers, while the processor is running in a power consumption state, in a time interval detected based on monitoring bus protocol events on the bus and knowledge of whether or not there is a pending transaction on the bus.

10. The system of claim 9 wherein the system bus is formed in a printed wiring board on which the processor and chipset ICs are installed as part of separate IC packages.

11. The system of claim 10 further comprising a display coupled to the chipset and a battery coupled to power the system, the system being integrated into a portable housing.

12. The system of claim 9 wherein the TUU is to monitor an arbitration event and a request phase on the bus.