Low leakage and data retention circuitry

• US 7,227,383 B2
• Filed: 01/20/2005
• Issued: 06/05/2007
• Est. Priority Date: 02/19/2004
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosid Delaware, Inc.
• Inventors: Cole, Andrew, Callahan, John M., Walker, William G., Zampaglione, Michael A., Hoberman, Barry A., Hillman, Daniel L.
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/041,687
• Publication Number:
  US 20050184758A1
• Time in Patent Office: 866 Days
• Field of Search: 326 93- 98, 326/46, 326/104, 326/112, 326/119, 326/121
• US Class Current: 326/93
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356086 with additional means for controlling the main nodes H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Claims

1. An integrated circuit comprising:

a first circuitry configured to receive input signals, receive a hold signal, process the input signals, retain data in a sleep state that has low leakage, and retain the data based on the hold; and

a sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

2. An integrated circuit comprising:

a first circuitry configured to receive input signals, process the input signals, and retain data in a sleep state that has low leakage, the first circuitry including master latch circuitry and slave latch circuitry, the slave latch circuitry being configured to retain the data in the sleep state; and

a sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

3. The integrated circuit of claim 2 wherein the slave latch circuitry comprises medium impedance transistors configured to bias sources in the slave latch circuitry.

4. The integrated circuit of claim 2 wherein the slave latch circuitry comprises stacked transistors configured to minimize leakage.

5. The integrated circuit of claim 2 wherein the slave latch circuitry comprises multiple threshold transistors configured to minimize leakage.

6. An integrated circuit comprising:

a first circuitry located within a power island and configured to receive input signals, process the input signals, and retain data in a sleep state that has low leakage; and

a sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

7. An integrated circuit comprising:

a first circuitry configured to receive input signals, process the input signals, and retain data in a sleep state that has low leakage;

a sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry; and

an adaptive leakage controller configured to determine the negative voltage of the sleep signal.

8. An integrated circuit comprising:

a first circuitry configured to receive a control signal to deactivate a sleep state, receive input signals, process the input signals, and retain data in the sleep state that has low leakage; and

a sleep transistor circuitry coupled to the first circuitry and configured to receive a sleep signal that has a negative voltage and reduce power consumption of the first circuitry in the state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

9. A method for operating an integrated circuit, the method comprising:

receiving input signals into first circuitry;

processing the input signals in the first circuitry;

retaining data in a sleep state that has low leakage in the first circuitry;

receiving a sleep signal that has a negative voltage into sleep transistor circuitry coupled to the first circuitry;

in the sleep transistor circuitry, reducing power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry;

receiving a hold signal into the first circuitry; and

retaining the data based on the hold signal.

10. A method for operating an integrated circuit, the method comprising:

receiving input signals into first circuitry that includes master latch circuitry and slave latch circuitry;

processing the input signals in the first circuitry;

retaining data in a sleep state that has low leakage in the first circuitry;

receiving a sleep signal that has a negative voltage into sleep transistor circuitry coupled to the first circuitry;

in the sleep transistor circuitry, reducing power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry; and

in the slave latch circuitry, retaining the data in the sleep state.

11. The method of claim 10 further comprising minimizing leakage using a medium impedance transistor to bias sources in the slave latch circuitry.

12. The method of claim 10 further comprising minimizing leakage using stacked transistors in the slave latch circuitry.

13. The method of claim 10 further comprising minimizing leakage using multiple threshold transistors in the slave latch circuitry.

14. The method of claim 10 wherein the first circuitry is located within a power island.

15. A method for operating an integrated circuit, the method comprising;

receiving input signals into first circuitry;

processing the input signals in the first circuitry;

retaining data in a sleep state that has low leakage in the first circuitry;

receiving a sleep signal that has a negative voltage into sleep transistor circuitry coupled to the first circuitry;

in the sleep transistor circuitry, reducing power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry; and

determining a negative voltage of the sleep signal in an adaptive leakage controller.

16. A method for operating an integrated circuit, the method comprising:

receiving input signals into first circuitry;

processing the input signals in the first circuitry;

retaining data in a sleep state that has low leakage in the first circuitry;

receiving a sleep signal that has a negative voltage into sleep transistor circuitry coupled to the first circuitry;

in the sleep transistor circuitry, reducing power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry; and

receiving a control signal to deactivate the sleep state in the first circuitry.