Dither scheme using pulse-density modulation (dither PDM)

• US 7,227,476 B1
• Filed: 08/14/2005
• Issued: 06/05/2007
• Est. Priority Date: 08/14/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wong, Hee
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US11/204,297
• Time in Patent Office: 660 Days
• Field of Search: 341/53, 341/72, 375/240, 375/238
• US Class Current: 341/53
• CPC Class Codes: H03M 5/08 Code representation by pulse width

Abstract

Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.

Claims

1. A pulse width modulator dithering circuit comprising:

a pulse-density modulator determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses from the pulse width modulator,

wherein the pulse-density modulator further comprises an adder receiving an input signal corresponding to a number of phase divisions to add to a predetermined number of output pulses from the pulse width modulator.

2. The circuit according to claim 1, wherein the adder increments a prior count by a value of the input signal.

3. A pulse width modulator dithering circuit comprising:

a pulse-density modulator determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses from the pulse width modulator,

wherein the pulse-density modulator further comprises a latch receiving a carry signal from the adder and clocked by the system clock, wherein an output from the latch is the signal received by the plus-one generator.

4. A pulse width modulator dithering circuit comprising:

a pulse-density modulator determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses from the pulse width modulator, wherein the plus-one generator further comprises;

a latch receiving the signal from the pulse-density modulator; and

a logic gate combining an output of the latch with an output from a pulse width modulator.

5. A pulse width modulator dithering circuit comprising:

a pulse-density modulator determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses from the pulse width modulator, wherein a leading edge of selected pulses from the pulse width modulator is advanced by the phase division.

6. An integrated circuit pulse width modulator including the circuit according to claim 5, the integrated circuit pulse width modulator further comprising:

a digital pulse width modulator producing a sequence of pulses each having a duration at least equal to a selected number of system clock periods, the dithering circuit advancing a duration of each of a plurality of pulses within the sequence.

7. A method of dithering a digital pulse width modulator output comprising:

receiving an input signal corresponding to a number of phase divisions to add to a predetermined number of output pulses from the pulse width modulator;

determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

advancing a width of selected output pulses from the pulse width modulator.

8. The method according to claim 7, further comprising:

incrementing a prior count by a value of the input signal.

9. The method according to claim 8, further comprising:

latching a carry signal from incrementing the prior count to produce a signal controlling selection of output pulses.

10. A method of dithering a digital pulse width modulator output comprising:

determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

advancing a width of selected output pulses from the pulse width modulator;

latching a signal controlling selection of output pulses from the pulse width modulator for width advancement; and

logically combining the latched signal with an output from a pulse width modulator.

11. A method of dithering a digital pulse width modulator output comprising:

determining a frequency at which an output of a pulse width modulator should be extended by a phase division for a system clock; and

advancing a width of selected output pulses from the pulse width modulator;

advancing a leading edge of selected pulses from the pulse width modulator by the phase division.

12. A digital pulse width modulator with dithering comprising:

a digital pulse width modulator producing a series of output pulses each having a duration equal to at least a selected number of system clock periods;

a pulse-density modulator determining a frequency at which output pulses within the series should be extended by a phase division for a system clock;

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses; and

an adder receiving an input signal corresponding to a number of phase divisions to add to a predetermined number of the output pulses from the digital pulse width modulator, the adder incrementing a prior count with a value of the received input signal and generating a carry output; and

a latch containing the prior count and a prior value of the carry signal, wherein the prior value of the carry signal is the signal received by the plus-one generator.

13. The digital pulse width modulator with dithering according to claim 12, wherein the plus-one generator further comprises:

a first logic gate combining an output of the pulse-density modulator with output pulses from the digital pulse width modulator;

a latch receiving an output of the first logic gate; and

a second logic gate combining an output of the latch with an output from a pulse width modulator.

14. The digital pulse width modulator with dithering according to claim 13, further comprising:

a multiplexer receiving the system clock and a plurality of phase-shifted versions of the system clock, wherein the latch receiving the signal from the pulse-density modulator is clocked by one of the phase-shifted versions of the system clock.

15. A digital pulse width modulator with dithering comprising:

a digital pulse width modulator producing a series of output pulses each having a duration equal to at least a selected number of system clock periods;

a pulse-density modulator determining a frequency at which output pulses within the series should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses,

wherein a leading edge of selected pulses within the series is advanced by the phase division.

16. A digital pulse width modulator with dithering comprising:

a digital pulse width modulator producing a series of output pulses each having a duration equal to at least a selected number of system clock periods;

a pulse-density modulator determining a frequency at which output pulses within the series should be extended by a phase division for a system clock; and

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses,

wherein a duration by which selected pulses are advanced equals a phase-division resolution of the digital pulse width modulator.

17. A digital pulse width modulator with dithering comprising:

a digital pulse width modulator producing a series of output pulses each having a duration equal to at least a selected number of system clock periods;

a pulse-density modulator determining a frequency at which output pulses within the series should be extended by a phase division for a system clock;

a plus-one generator receiving a signal from the pulse-density modulator and advancing a width of selected output pulses; and

a digital dead-time controller employing the system clock and a plurality of phase-shifted versions of the system clock to provide dead-time delays in an output.