NAND flash memory device capable of improving read speed
First Claim
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1. A NAND flash memory device including a main field and a redundant field comprising:
- a first page buffer circuit reading main data bits from the main field during a read operation;
a second page buffer circuit reading redundant data bits from the redundancy field during the read operation;
a first column gate circuit configured to select a part of the main data bits read from the main field and at the same time a part of the redundant data bits read from the redundant field in response to first column selection signals; and
a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.
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Abstract
A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.
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Citations
15 Claims
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1. A NAND flash memory device including a main field and a redundant field comprising:
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a first page buffer circuit reading main data bits from the main field during a read operation; a second page buffer circuit reading redundant data bits from the redundancy field during the read operation; a first column gate circuit configured to select a part of the main data bits read from the main field and at the same time a part of the redundant data bits read from the redundant field in response to first column selection signals; and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A NAND flash memory device including a main field and a redundant field comprising:
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a first page buffer circuit reading main data bits form the main field during a read operation; a second page buffer circuit reading redundant data bits from the redundant field during the read operation; a column decoder circuit generating first column selection signals and second column selection signals in response to a column address; a first column gate circuit configured to simultaneously select a part of the main data bits read from the main field and a part of the redundant data bits read from the redundant field in response to the first column selection signals; a second column gate circuit configured to select a part of the selected main data bits in response to the second column selection signals; a multiplexer circuit receiving main data bits from the second column gate circuit, and redundant data bits from the first column gate circuit; and a redundancy control circuit configured to control the multiplexer circuit in response to the column address. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A reading method of a NAND flash memory device having a main field and a redundancy field comprising:
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simultaneously reading main data bits from the main field and redundant data bits from the redundant field during a read operation; generating first column selection signals and second column selection signals in response to a column address; simultaneously selecting a part of the main data bits read from the main field and a part of the redundant data bits read from the redundant field in response to the first column selection signals; selecting a part of the selected main data bits in response to the second column selection signals; and selectively outputting main data bits and redundant data bits in accordance with redundancy information. - View Dependent Claims (15)
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Specification