Clock data recovery circuitry associated with programmable logic device circuitry
DCFirst Claim
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1. Apparatus for receiving and processing a CDR signal comprising:
- PLD circuitry;
first input circuitry configured to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream;
second input circuitry configured to receive an external reference clock signal, wherein the external reference clock signal has a frequency related to a frequency of the embedded clock signal; and
processing circuitry at least partly controlled by the PLD circuitry and configured to use the external reference clock signal to recover the data information from the CDR signal.
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Abstract
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
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Citations
138 Claims
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1. Apparatus for receiving and processing a CDR signal comprising:
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PLD circuitry; first input circuitry configured to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream; second input circuitry configured to receive an external reference clock signal, wherein the external reference clock signal has a frequency related to a frequency of the embedded clock signal; and processing circuitry at least partly controlled by the PLD circuitry and configured to use the external reference clock signal to recover the data information from the CDR signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. Apparatus for producing and transmitting a CDR signal comprising:
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PLD circuitry configured to produce data information and a PLD clock signal; input circuitry configured to receive an external reference clock signal; buffer circuitry configured to buffer the data information between a clock regime associated with the PLD clock signal and a different clock regime associated with the external reference clock signal, wherein the clock regimes have different frequencies; and output circuitry configured to use the reference clock signal to produce the CDR signal including the data information and an embedded clock signal having a frequency related to the external reference clock signal. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. Apparatus for receiving an information signal which includes data information having clock information for the data information embedded in the data information comprising:
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first input circuitry configured to receive the information signal; circuitry configured to receive a programmable scale factor; second input circuitry configured to receive an external reference clock signal having a reference frequency which is related to a frequency of the clock information by the programmable scale factor; reference clock signal processing circuitry configured to use the information signal and the reference clock signal to produce a recovered clock signal having phase and frequency which respectively correspond to a phase and a frequency of the clock information; and data recovery circuitry configured to use the recovered clock signal and the information signal to produce a data output signal indicative of the data information in the information signal. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. Apparatus for transmitting an information signal which includes data information having clock information for the data information embedded in the data information comprising:
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circuitry configured to receive a programmable scale factor; input circuitry configured to receive an external reference clock signal having a reference frequency which is related to a frequency of the clock information by the programmable scale factor; reference clock signal processing circuitry configured to use the external reference clock signal to produce a further reference clock signal having the frequency of the clock information; data source circuitry configured to produce a data signal indicative of the data information; and data signal processing circuitry configured to process the data signal in accordance with the further reference clock signal to produce the information signal. - View Dependent Claims (70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98)
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99. Programmable serializer circuitry comprising:
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control circuitry that receives a programmable number; input circuitry that receives the programmable number of input signals in parallel; and output circuitry that produces an output signal that is serially indicative of the programmable number input signals one after another. - View Dependent Claims (100, 101, 102, 103, 104, 105, 106, 107, 108)
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109. Programmable deserializer circuitry comprising:
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control circuitry that receives a programmable number; input circuitry that receives an input signal serially indicative of plural bits of information one after another and stores the programmable number of successive ones of those bits; and output circuitry that produces the programmable number of output signals in parallel, each of the output signals being indicative of a respective one of the bits stored by the input circuitry. - View Dependent Claims (110, 111, 112, 113, 114, 115, 116, 117, 118)
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119. Apparatus for receiving and processing a plurality of CDR signals, each of which includes data information and clock information, comprising:
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first circuitry producing a plurality of candidate recovered clock signals from a reference clock signal, the candidate recovered clock signals having phases that are shifted relative to one another; and a plurality of second circuitries, each receiving a respective one of the CDR signals and using the candidate reference clock signals to recover the clock information from the CDR signal received by that second circuitry. - View Dependent Claims (120, 121, 122, 123, 124)
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125. Apparatus for receiving and processing a CDR signal comprising:
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first input circuitry operative to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream; second input circuitry operative to receive a reference clock signal, wherein the reference clock signal has a frequency related to a frequency of the embedded clock signal; phase locked loop circuitry operative to use the reference clock signal to generate a recovered clock signal having a frequency equal to the frequency of the embedded clock signal; and processing circuitry operative to use the recovered clock signal to recover the data information from the CDR signal. - View Dependent Claims (126, 127, 128, 129, 130, 131, 132, 133)
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134. Apparatus for producing and transmitting a CDR signal comprising:
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first input circuitry operative to receive a reference clock signal; second input circuitry operative to receive a data information signal; phase locked loop circuitry operative to use the reference clock signal to generate an embedded clock signal; buffer circuitry operative to buffer the data information between a clock regime associated with the data information and a clock regime associated with the embedded clock signal, wherein the clock regimes have different frequencies; and output circuitry operative to use the embedded clock signal to produce the CDR signal from the data information signal. - View Dependent Claims (135, 136, 137, 138)
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Specification