DC offset reduction in radio-frequency apparatus and associated methods

• US 7,228,109 B2
• Filed: 02/12/2002
• Issued: 06/05/2007
• Est. Priority Date: 01/12/2001
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Kerth, Donald A., Srinivasan, Vishnu S., Paulus, Tod
• Primary Examiner(s): Urban; Edward F.
• Assistant Examiner(s): Lee; John J.
• Application Number:
  US10/074,676
• Publication Number:
  US 20030063690A1
• Time in Patent Office: 1,939 Days
• Field of Search: 455/88, 455/74, 455/552.1, 455/86, 455/78, 455/87, 455/553.1, 455/556.1, 455/137, 455/139, 455/234.2, 455/187.1, 455/189.1, 455/190.1, 455/164.1, 455/255, 455/239.1, 455/76, 455/550.1, 455/131, 455/230, 455/234.1, 455/236.1, 455/251.1, 455/333, 455/334, 455/260, 455/208, 375/334, 375/316, 375/322, 375/259
• US Class Current: 455/74
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.

Claims

1. A radio-frequency (RF) receiver circuitry, comprising:

down-converter circuitry configured to accept a received radio-frequency signal, the down-converter circuitry further configured to process the received radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal;

analog-to-digital converter (ADC) circuitry configured to receive the in-phase and quadrature down-converted signals and to provide an in-phase digital output signal and a quadrature digital output signal;

DC offset reduction circuitry coupled to the analog-to-digital converter circuitry,

wherein the DC offset reduction circuitry tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals; and

a combiner circuitry configured to provide to the analog-to-digital circuitry an in-phase difference signal and a quadrature difference signal,

wherein the combiner circuitry subtracts an in-phase output signal of the DC offset reduction circuitry from the in-phase down-converted signal to produce the in-phase difference signal, and

wherein the combiner circuitry subtracts a quadrature output signal of the DC offset reduction circuitry from the quadrature down-converted signal to produce the quadrature difference signal.

2. The radio-frequency receiver circuitry of claim 1, wherein the DC offset reduction circuitry further comprises a digital-to-analog circuitry configured to provide the in-phase and quadrature output signals of the DC offset reduction circuitry.

3. The radio-frequency receiver circuitry of claim 2, wherein the DC offset reduction circuitry further comprises a filter circuitry configured to process the in-phase and quadrature digital output signals to provide an in-phase filtered digital output signal and a quadrature filtered digital output signal, the filter circuitry further configured to provide the in-phase and quadrature filtered digital output signals to the digital-to-analog circuitry.

4. The radio-frequency receiver circuitry of claim 3, wherein a transfer function of the DC offset reduction circuitry has at least one pole the location of which is adjustable over an adjustment cycle of the DC offset reduction circuitry.

5. The radio-frequency receiver circuitry of claim 4, wherein the location of the at least one pole is adjusted in an initial part of the adjustment cycle of the DC offset reduction circuitry so that the DC offset reduction circuitry tends to settle quickly.

6. The radio-frequency receiver circuitry of claim 5, wherein the location of the at least one pole is further adjusted in a later part of the adjustment cycle of the DC offset reduction circuitry so that the DC offset reduction circuitry tends to remove the DC offset more accurately.

7. The radio-frequency receiver circuitry of claim 6, wherein the location of the at least one pole is adjusted by modifying a gain of the DC offset reduction circuitry.

8. The radio-frequency receiver circuitry of claim 7, wherein the location of the at least one pole is adjusted before a reception of a burst of data begins.

9. The radio-frequency receiver circuitry of claim 8, wherein the in-phase and quadrature output signals of the DC offset reduction circuitry become substantially constant before the reception of the burst of data begins.

10. The radio-frequency receiver circuitry of claim 9, wherein the filter circuitry comprises a digital filter circuitry.

11. The radio-frequency receiver circuitry of claim 10, wherein the digital filter circuitry comprises a low-pass filter circuitry.

12. The radio-frequency receiver circuitry of claim 11, wherein the low-pass filter circuitry comprises an integrator circuitry.

13. The radio-frequency receiver circuitry of claim 12, wherein the analog-to-digital converter circuitry comprises a sigma-delta analog-to-digital converter circuitry.

14. The radio-frequency receiver circuitry of claim 13 used in a radio-frequency transceiver circuitry.

15. The radio-frequency receiver circuitry of claim 13 used in a low intermediate-frequency (IF) radio-frequency receiver circuitry.

16. A radio-frequency (RF) receiver circuitry, comprising:

receiver analog circuitry included within a first integrated circuit, the receiver analog circuitry, comprising;

down-converter circuitry configured to receive and down-convert a radio-frequency input signal to generate a down-converted signal;

an analog-to-digital converter circuitry to convert the down-converted signal to a digital output signal; and

DC offset reduction circuitry coupled to the analog-to-digital converter circuitry, wherein the DC offset reduction circuitry tends to reduce a DC offset of the receiver analog circuitry;

receiver digital circuitry included within a second integrated circuit, the receiver digital circuitry configured to receive and process the digital output signal to generate a processed digital signal; and

a combiner circuitry configured to provide a difference signal to the analog-to-digital circuitry, wherein the combiner circuitry subtracts an output signal of the DC offset reduction circuitry from the down-converted signal to produce the difference signal.

17. The radio-frequency receiver circuitry of claim 16, wherein the DC offset reduction circuitry further comprises a feedback loop that includes a cascade coupling of a filter circuitry and a digital-to-analog circuitry, wherein the filter circuitry receives the digital output signal, and wherein the digital-to-analog circuitry provides the output signal of the DC offset reduction circuitry.

18. The radio-frequency receiver circuitry of claim 17, wherein a transfer function of the DC offset reduction circuitry has at least one pole the location of which is adjustable so as to modify the settling time of the DC offset reduction circuitry.

19. The radio-frequency receiver circuitry of claim 18, wherein the location of the at least one pole is adjusted at an initial point in time so that the DC offset reduction circuitry tends to settle quickly.

20. The radio-frequency receiver circuitry of claim 19, wherein the location of the at least one pole is adjusted at least once more after the initial point in time so that the DC offset reduction circuitry tends to reduce the DC offset more accurately.

21. The radio-frequency receiver circuitry of claim 20, wherein the location of the at least one pole is adjustable by modifying a gain of the DC offset reduction circuitry.

22. The radio-frequency receiver circuitry of claim 21, wherein adjustment of the location of the at least one pole completes before a reception of a burst of data by the receiver analog circuitry begins.

23. The radio-frequency receiver circuitry of claim 22, used within a radio-frequency transceiver circuitry.

24. The radio-frequency receiver circuitry of claim 22, further comprising programmable gain amplifier circuitry coupled to the combiner circuitry and to the analog-to-digital circuitry, the programmable gain amplifier circuitry configured to apply a programmable gain to the difference signal to produce an amplified difference signal, the programmable gain amplifier circuitry further configured to provide the amplified difference signal to the analog-to-digital converter circuitry.

25. The radio-frequency receiver circuitry of claim 24, used within a radio-frequency transceiver circuitry.

26. A method of receiving a radio-frequency (RF) signal, comprising:

down-converting the radio-frequency signal within a receiver analog circuitry to generate a down-converted signal;

converting the down-converted signal to a digital output signal by using an analog-to-digital converter circuitry that resides within the receiver analog circuitry; and

feeding back to an input of the analog-to-digital converter circuitry a feedback signal that relates to the digital output signal, by subtracting the feedback signal from the down-converted signal to generate a difference signal and supplying the difference signal to the input of the analog-to-digital converter circuitry,

wherein feeding back the feedback signal to an input of the analog-to-digital converter tends to reduce a DC offset of the receiver analog circuitry.

27. The method of claim 26, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises:

filtering the digital output signal to generate a filtered digital signal; and

converting the filtered digital signal to the feedback signal by using a digital-to-analog converter circuitry.

28. The method of claim 27, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry comprises adjusting a location of at least one pole within the receiver analog circuitry.

29. The method of claim 28, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises adjusting at an initial point in time the location of the at least one pole so that the DC offset tends to be reduced quickly.

30. The method of claim 29, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises adjusting the location of the at least one pole at least once more after the initial point in time so that the DC offset tends to be reduced accurately.

31. The method of claim 30, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises adjusting the location of the at least one pole by modifying a gain within the receiver analog circuitry.

32. The method of claim 31, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises completing the adjustment of the location of the at least one pole before a reception of a burst of data by the receiver analog circuitry begins.

33. The method of claim 32, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises holding substantially constant the feedback signal before a reception of a burst of data begins.

34. The method of claim 33, wherein feeding back the feedback signal to the input of the analog-to-digital converter circuitry further comprises:

applying a programmable gain to the difference signal to produce an amplified difference signal; and

supplying the amplified difference signal to the input of the analog-to-digital converter circuitry.

35. The method of claim 34, wherein converting the down-converted signal to a digital output signal comprises using a sigma-delta analog-to-digital converter circuitry that resides within the receiver analog circuitry.

36. The method of claim 35, further comprising supplying the digital output signal to a receiver digital circuitry.

37. The method of claim 36, further comprising processing the digital output signal in the receiver digital circuitry to generate a baseband signal.

38. The method of claim 37, further comprising providing the baseband signal to a baseband processor circuitry.

39. The method of claim 38, wherein receiving the radio-frequency signal further comprises receiving the radio-frequency signal within a low intermediate-frequency radio-frequency receiver circuitry.

40. The method of claim 39, wherein receiving the radio-frequency signal further comprises receiving the radio-frequency signal within a radio-frequency transceiver circuitry.