Managing instruction side-effects

• US 7,228,404 B1
• Filed: 09/28/2000
• Issued: 06/05/2007
• Est. Priority Date: 01/18/2000
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Mansingh, Sanjay, Campbell, Paul William, Patel, Ronak, Van Dyke, Korbin S., Ramesh, T.R., Thusoo, Shalesh, Saund, Gurjeet Singh
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US09/672,440
• Time in Patent Office: 2,441 Days
• Field of Search: 712/209, 712/227, 712/228, 712/220
• US Class Current: 712/228
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.

Claims

1. A method, comprising the steps of:

during execution of an instruction on a computer, in response to an operation of the instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, storing a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and resuming the execution without generating the architecturally-visible side-effect;

later writing the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

2. The method of claim 1, wherein the later writing is triggered by a read of the architecturally-visible storage location.

3. The method of claim 1, wherein the later writing is triggered by the completion of the execution of the instruction.

4. The method of claim 1, wherein the architecturally-visible storage location includes at least two of a floating-point instruction pointer, a floating-point data pointer, and a floating-point opcode.

5. The method of claim 1, wherein the representative value is held in a temporary register until several other side-effects are also ready to be committed to the architecturally-visible storage location simultaneously.

6. The method of claim 1, wherein the representative value is held in a non-addressable storage register, and a process of the instruction only cedes control on an instruction boundary, so that the non-addressable information is not lost.

7. The method of claim 1,

context switch software programmed to store a context of a first process and to load a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution;

a multi-stage execution pipeline of a computer, at least some instructions executed in the pipeline maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

8. The method of claim 1,

during hardware execution of an instruction stream including the instruction, recognizing a condition that is a superset of a condition being monitored for occurrence, and raising a first exception as a result of recognizing the superset condition;

in software, filtering the superset condition to determine whether the monitored condition has occurred;

if the monitored condition has occurred, establishing a second exception to be raised after execution of further instructions of the instruction stream.

9. A computer, comprising:

circuitry designed to recognize an operation of an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, and in response, to store a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and to resume the execution without generating the architecturally-visible side-effect;

circuitry and/or software designed to later write the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

10. The computer of claim 9, further comprising:

circuitry designed to recognize a condition in which a second instruction is to affect the execution of a third instruction, and in response, to set the processor into single-step mode;

circuitry designed to raise a single-step exception after executing the second instruction, and to set the processor out of single-step mode.

11. The computer of claim 9, wherein the storage location is a location in main memory or a cache memory of the computer.

12. The computer of claim 9, wherein the storage location is a general purpose register of the computer having no address in an address space of the computer.

13. A method, comprising the steps of:

storing a context of a first process and loading a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution;

at least some instructions executed in a multi-stage execution pipeline of the computer maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

14. The computer of claim 13, comprising:

recognizing a condition that is a superset of a condition being monitored for occurrence, and raising a first exception as a result of recognizing the superset condition;

in software, filtering the superset condition to determine whether the monitored condition has occurred;

if the monitored condition has occurred, establishing a second exception to be raised after execution of further instructions of the instruction stream.

15. The computer of claim 13, comprising:

recognizing a condition in which an instruction is to affect the execution of a second instruction, and in response, setting the processor into single-step mode;

taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode.

16. A computer, comprising:

context switch software programmed to store a context of a first process and to load a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution;

a multi-stage execution pipeline of a computer, at least some instructions executed in the pipeline maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

17. The computer of claim 16, comprising:

circuitry designed to recognize an operation of an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, and in response, to store a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and to resume the execution without generating the architecturally-visible side-effect;

circuitry and/or software designed to later write the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

18. The computer of claim 16, wherein the instructions are marked by a marker on a last of the instructions generated by decoding an external-form instruction fetched from memory.

19. The computer of claim 18, wherein the context switch is triggered in response to an action of a non-final one of the instructions generated by decoding.

20. The computer of claim 16, wherein the instructions are marked by a marker on an intermediate one of the instructions generated by decoding an external-form instruction fetched from memory, the marker indicating an iteration boundary of an external-form instruction specifying repeated execution of an operation.

21. The computer of claim 16, further comprising the step of:

based on the memory protection check of a younger of the instructions executing in the pipeline, canceling the effect of an older of the instructions.

22. A method, comprising the steps of:

during hardware execution of an instruction stream, recognizing a condition that is a superset of a condition whose occurrence is desired to be detected, and raising a first exception as a result of recognizing the superset condition;

in software, filtering the superset condition to determine whether the desired condition has occurred, and if so, gathering further information about the condition;

if the desired condition is determined to have occurred, establishing a second exception to be raised after execution of further instructions of the instruction stream, and making the further information available for a handler of the second exception.

23. The method of claim 22, comprising:

recognizing a condition in which an instruction is to affect the execution of a second instruction, and in response, setting the processor into single-step mode;

taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode.

24. A computer, comprising:

an instruction execution pipeline designed to execute instructions, and to monitor the executing instructions for a condition arising during execution that is a superset of a condition whose occurrence is desired to be detected, and to raise a first exception as a result of recognizing the superset condition;

software designed to filter the superset condition to determine whether the monitored condition has occurred, and if the monitored condition is determined to have occurred, to gather further information about the condition, and to establish a second exception to be raised after execution of further instructions of the instruction stream, and to make the further information available for a handler of the second exception.

25. The computer of claim 24, further comprising:

circuitry designed to recognize an operation of an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, and in response, to store a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and to resume the execution without generating the architecturally-visible side-effect; and

circuitry and/or software designed to later write the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

26. The computer of claim 24:

further comprising context switch software programmed to store a context of a first process and to load a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution;

wherein at least some instructions executed in the pipeline maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

27. The computer of claim 24, wherein the desired condition is a memory reference to a narrow range of addresses, and the superset condition is a memory reference to a broader range of addresses.

28. The computer of claim 27, wherein the broader range of addresses is a cache line.

29. The computer of claim 24, wherein the monitored condition is a memory reference to an address of a reference class, and the superset condition is a memory reference to the address, without respect to reference class.

30. The computer of claim 24, wherein the filtering software records the nature of the monitored condition that has occurred.

31. The computer of claim 24, wherein the filtering software records multiple occurrences of desired conditions before the second exception is raised.

32. The computer of claim 24, wherein the second exception vectors to a debug entry point of an operating system.

33. The computer of claim 24, wherein the condition is an exception recognized on one of a plurality of instructions generated by a single instruction fetched from a memory, and the second exception is deferred until an instruction boundary of the instruction fetched from memory.

34. A method, comprising the steps of:

during execution of a program on a computer, recognizing in hardware a condition in which an instruction is to affect the function to be performed by a second instruction, and in response, setting the processor into single-step mode;

taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode.

35. The method of claim 34, further comprising the steps of:

in response to an operation of the instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, storing a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and resuming the execution without generating the architecturally-visible side-effect;

later writing the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

36. A computer, comprising:

hardware designed to recognize a condition rising during execution of an instruction on a computer, in which the instruction is to affect the function to be performed by a second instruction;

hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and

hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode.

37. The computer of claim 36, further comprising:

context switch software programmed to store a context of a first process and to load a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution;

a multi-stage execution pipeline of a computer, at least some instructions executed in the pipeline maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

38. The computer of claim 36, further comprising:

an instruction execution pipeline designed to execute instructions, and to monitor the executing instructions for a condition arising during execution that is a superset of a condition whose occurrence is desired to be detected, and to raise a first exception as a result of recognizing the superset condition;

software designed to filter the superset condition to determine whether the monitored condition has occurred, and if the monitored condition is determined to have occurred, to establish a second exception to be raised after execution of further instructions of the instruction stream.

39. The computer of claim 36, wherein the first instruction writes a stack segment register.

42. The computer of claim 36, wherein the first and second instructions are generated by a decoder for a complex instruction set in response to decoding a single instruction of the complex instruction set.

43. The computer of claim 42, wherein the second instruction lies on a boundary between iterations of a loop executed within the single complex instruction.

44. The computer of claim 36, wherein servicing a single-step exception includes querying a debug touch record.

45. The computer of claim 36, wherein the first instruction writes an interrupt enable flag of the computer.

40. A computer, comprising:

hardware designed to recognize a condition rising during execution of an instruction on a computer, in which the instruction is to affect the execution of a second instruction, wherein the first instruction and second instructions are generated by an instruction decoder in response to a single instruction fetched from a memory;

hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and

hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode.

41. The computer of claim 40, wherein the first instruction writes to a group of interrupt flags.

46. A method, comprising the steps of:

during execution of a program on a computer, recognizing in hardware a juxtaposition in memory of first and second instructions is to affect the function to be performed by the two instructions, and in response, setting the processor into single-step mode;

taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode.

47. The method of claim 46, further comprising the steps of:

during execution of an instruction of the program, in response to an operation of the instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, storing a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and resuming the execution without generating the architecturally-visible side-effect;

later writing the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.

48. The method of claim 46, further comprising the steps of:

storing a context of a first process and loading a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution, the program executing in the first or second process;

at least some instructions executed in a multi-stage execution pipeline of the computer maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

49. The method of claim 46, further comprising the steps of:

during hardware execution of the program, recognizing in hardware a condition that is a superset of a condition whose occurrence is desired to be detected, and raising a first exception as a result of recognizing the superset condition;

in software, filtering the superset condition to determine whether the desired condition has occurred, and if so, gathering further information about the condition;

if the desired condition is determined to have occurred, establishing a second exception to be raised after execution of further instructions of the instruction stream, and making the further information available for a handler of the second exception.

50. A computer, comprising:

hardware designed to recognize a condition rising during execution of instructions on a computer, the condition being a juxtaposition in memory of first and second instructions is to affect the function to be performed by the two instructions;

hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and

hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode.

51. The computer of claim 50, wherein the first instruction writes to a group of interrupt flags.

52. The computer of claim 50, wherein the first instruction writes an interrupt enable flag of the computer.