Semiconductor integrated circuit device, program delivery method, and program delivery system

• US 7,228,436 B2
• Filed: 07/03/2003
• Issued: 06/05/2007
• Est. Priority Date: 10/31/2002
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kawaguchi, Kenichi
• Primary Examiner(s): Song; Hosuk
• Assistant Examiner(s): SHAN, APRIL YING
• Application Number:
  US10/611,879
• Publication Number:
  US 20040088554A1
• Time in Patent Office: 1,433 Days
• Field of Search: 713/189, 713/193, 235/492, 380/277
• US Class Current: 713/189
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation

Abstract

When an encrypted program and a decryption program are inputted to a first memory, a semiconductor integrated circuit device causes a bus port to disable access from the outside and enables access to the first memory and to a second memory, thereby transferring the encrypted program and the decryption program from the first memory to the second memory. When the transfer is completed, the semiconductor integrated circuit device disables access to the first memory and gives, to a CPU, an instruction to decrypt the encrypted program by using a secret key held in a secret key holder and the decryption program and execute the decrypted program. After the execution of the decrypted program is completed, the semiconductor integrated circuit device disables access to the second memory.

Claims

1. A semiconductor integrated circuit device comprising:

a first RAM for inputting and outputting data between a bus and itself;

a second RAM for inputting and outputting data between the bus and itself;

a secret key holder for holding a secret key;

a bus port for controlling access from outside to the bus;

a CPU for storing an encrypted program and a decryption program in the first memory RAM via the bus port, decrypting the encrypted program by using the decryption program and the secret key, and executing the decrypted program; and

a controller for causing, the bus port to disable access from the outside and enable access to the first and second RAMs when the encrypted program and the decryption program are stored in the first RAM, thereby transferring the encrypted program and the decryption program from the first RAM to the second RAM,

disabling access to the first RAM when the transfer is completed, and

disabling access to the second RAM when the decryption and the execution of the decrypted program are completed.

2. The semiconductor integrated circuit device of claim 1, further comprising:

a secret key access port for controlling access from the CPU to the secret key holder, wherein

the secret key access port enables access to the secret key holder when the transfer is completed and disables access to the secrete key holder when the execution of the decrypted program is completed.

3. The semiconductor integrated circuit device of claim 1, wherein the CPU includes a register and erases data stored in the register if the execution of the decrypted program is completed.

4. The semiconductor integrated circuit device of claim 1, wherein the controller controls access to the first and second RAMs by controlling chip select signals to the first and second RAMs.

5. The semiconductor integrated circuit device of claim 1, wherein

the controller includes a flag storing portion for storing first and second flags, enables access to the first and second RAMs when the first flag is set, disables access to the first RAMs when the first flag is reset and the second flag is set, and disables access to the second RAMs when each of the first and second flags is reset,

the bus port disables access from the outside when at least one of the first and second flags is set, and

the CPU sets the first and second flags when the encrypted program and the decryption program are inputted to the first RAM, resets the first flag when the transfer is completed, and resets the second flag when the execution of the decrypted program is completed.

6. A semiconductor integrated circuit device comprising:

a first RAM for inputting and outputting data between a bus and itself;

a second RAM for inputting and outputting data between the bus and itself;

a first RAM port connected between the bus and the first RAM to control access from the bus to the first RAM;

a second RAM port connected between the bus and the second RAM to control access from the bus to the second RAM;

a secret key holder for holding a secret key;

a bus port for controlling access from outside to the bus;

a CPU having a register, the CPU writing an encrypted program and a decryption program in the first RAM via the bus port, decrypting the encrypted program by using the decryption program and the secret key, writing the decrypted program in the second RAM, and executing the decrypted program; and

a controller for causing the bus port to disable access from the outside to the bus, the first RAM port to disable the writing to the first RAM, and the second RAM port to enable access to the second RAM when the writing to the first memory is completed and

causing, when the execution of the decrypted program is completed, the CPU to erase data stored in the register and disable access to the secrete key holder, while causing the second RAM port to disable access to the second RAM.

7. A semiconductor integrated circuit device comprising:

a first RAM for inputting and outputting data between a bus and itself;

a second RAM for inputting and outputting data between the bus and itself;

a RAM port connected between the bus and the first memory to control access from the bus to the first RAM;

a secret key holder for holding a secret key;

a bus port for controlling access from outside to the bus;

a CPU having a register, the CPU writing an encrypted program and a decryption program in the first RAM via the bus port, decrypting the encrypted program by using the decryption program and the secret key, writing the decrypted program in the second RAM, and executing the decrypted program; and

a controller including a RAM initializer for erasing data in the second RAM, the controller causing, when the wiring to the first RAM is completed, the bus port to disable access from the outside to the bus and causing the memory port to disable the writing to the first RAM and

causing, when the execution of the decrypted program is completed, the CPU to erase data stored in the register and disable access to the secret key holder and causing the RAM initializer to erase the data in the second RAM.

8. A semiconductor integrated circuit device comprising:

a first RAM for inputting and outputting data between a bus and itself;

a second RAM for inputting and outputting data between the bus and itself;

a secret key holder for holding a secret key;

a decryption key holder for holding a decryption key;

a bus port for controlling access from outside to the bus;

a CPU including a register, the CPU performing first storage for storing the encrypted decryption key and a decryption key decryption program in the first RAM via the bus port, performing first decryption for decrypting the encrypted decryption key by using the decryption key decryption program and the secret key, writing the decrypted decryption key in the decryption key holder, performing second storage for storing an encrypted program and a decryption program in the first RAM, performing decryption for decrypting the encrypted program by using the decryption program and the decrypted decryption key, and executing the decrypted program; and

a controller for causing, when the first storage to the first RAM is completed, the bus port to disable access from the outside to the bus and enabling access to the first and second RAMs such that the encrypted decryption key and the decryption key decryption program are transferred from the first RAM to the second RAM,

enabling, when the transfer is completed, access to the secret key holder and disabling access to the first RAM;

causing, when the first decryption is completed, the CPU to erase data stored in register and disable access to the secret key holder, while disabling access to the second RAM, enabling access to the first RAM, and causing the bus port to enable access from the outside to the bus,

causing, when the second storage to the first RAM is completed, the bus port to disable access from the outside to the bus and enabling access to the second RAM such that the encrypted program and the decryption program are transferred from the first RAM to the second RAM,

enabling, when the transfer is completed, access to the decryption key holder and disabling access to the first RAM, and

causing, when the second decryption and the execution of the decrypted program are completed, the CPU to erase data stored in the register and disable access to the secret key holder and disabling access to the second RAM.