Circuit operation verification device and method
First Claim
1. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
- a plurality of simulation sections, each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided;
a bus for connecting the plurality of simulation sections to enable mutual communications;
a bus controller for controlling the bus; and
to a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified,wherein the circuit comprises a plurality of circuit units, each of which comprises at least one circuit element, wherein the plurality of circuit units is divided based on a temporal communication occurrence pattern among the plurality of circuit units to generate the plurality of simulation sections, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus.
1 Assignment
0 Petitions
Accused Products
Abstract
A circuit verification device includes emulators to which circuit portions obtained by dividing the circuit are implemented. The emulators communicate with each other through a bus to verify the functional operation of the circuit. The circuit is divided based on a communication occurrence pattern between circuit units so that the number of communications occurring between circuit portions is minimized. The input signals of the bus are preferably arranged in the bus address space in descending order of a signal change rate, and a burst transfer may be utilized. Through paths within the circuit being verified are searched, and a plurality of circuit units is divided so as to minimize the number of through paths among the circuit portions.
8 Citations
29 Claims
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1. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a plurality of simulation sections, each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided; a bus for connecting the plurality of simulation sections to enable mutual communications; a bus controller for controlling the bus; and to a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified, wherein the circuit comprises a plurality of circuit units, each of which comprises at least one circuit element, wherein the plurality of circuit units is divided based on a temporal communication occurrence pattern among the plurality of circuit units to generate the plurality of simulation sections, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a plurality of simulation sections each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided; a bus for connecting the plurality of simulation sections to enable mutual communications; a bus controller for controlling the bus; and a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified, wherein any of the plurality of simulation sections and the bus controller is allowed to be a bus master for communications, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus.
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12. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a plurality of simulation sections, each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided; a bus for connecting the plurality of simulation sections to enable mutual communications; a bus controller for controlling the bus; and a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified, wherein each of the plurality of simulation sections arranges input signals from the bus and output signals to the bus in a bus address space in descending order of a signal change rate, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus.
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13. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a plurality of simulation sections, each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided; a bus for connecting the plurality of simulation sections to enable mutual communications; a bus controller for controlling the bus; and a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified, wherein signals of through paths existing among the plurality of simulation sections are bundled and placed in a portion of the bus address space in each of the plurality of simulation sections, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus. - View Dependent Claims (14)
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15. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a plurality of simulation sections, each simulating functional operations of a corresponding circuit portion of a plurality of circuit portions into which the circuit is divided; a bus for connecting the plurality of simulation sections to enable mutual communications; a bus controller for controlling the bus; and a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified, wherein the circuit comprises a plurality of circuit units, each of which comprises at least one circuit element, wherein the plurality of circuit units is divided so that the number of through paths among the plurality of simulation sections is minimized, to generate the plurality of simulation sections, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus.
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16. A circuit operation verification method for verifying by simulation a functional operation of a circuit to be verified, comprising:
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a) dividing the circuit into a plurality of circuit portions based on a temporal communication occurrence pattern among the plurality of circuit portions when the circuit is divided into the plurality of circuit portions; b) connecting a plurality of simulation circuits so as to enable mutual communication via a bus, wherein each of the plurality of simulation circuits simulate functional operations of a corresponding circuit portion of the plurality of circuit portions; and c) verifying the functional operation of the circuit by communicating among the plurality of simulation circuits, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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25. A computer-readable medium containing a program for causing a computer to verify by simulation a functional operation of a circuit to be verified, the program, when executed, causing the computer to perform steps comprising:
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a) dividing the circuit into a plurality of circuit portions so that the number of communications among the plurality of circuit portions is minimized when the circuit is divided into the plurality of circuit portions; b) connecting a plurality of simulation circuits so as to enable mutual communication via a bus, wherein the plurality of simulation circuits each simulate functional operations of a corresponding circuit portion of the plurality of circuit portions; and c) verifying the functional operation of the circuit by communicating among the plurality of simulation circuits, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received via the bus. - View Dependent Claims (26, 27, 28, 29)
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Specification