Method and apparatus for a semiconductor device with a high-k gate dielectric

• US 7,229,893 B2
• Filed: 12/23/2004
• Issued: 06/12/2007
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chih-Hao, Chen, Shang-Chih, Tsai, Ching-Wei
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US11/021,269
• Publication Number:
  US 20050287759A1
• Time in Patent Office: 901 Days
• Field of Search: 438/424, 257/E21.546
• US Class Current: 438/424
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

shallow trench isolation regions formed in the substrate to define active device regions between the isolation regions;

a counter-doping channel region formed on the surface of semiconductor substrate, overlying at least one of the active areas wherein the counter-doping channel region is doped with its type different from the semiconductor substrate;

at least one region of high-k gate dielectric material formed over the substrate, and having a top surface and sidewalls;

at least one region of gate electrode material formed over the top surface of the gate dielectric region and having non-high-k sidewalls coextensive with the sidewalls of the gate dielectric region; and

sidewall spacer material formed over the gate electrode sidewalls and the gate dielectric sidewalls and extending into the surface of the substrate or into the shallow trench isolation regions, respectively, below the bottom layer of the gate dielectric region.

2. The semiconductor device according to claim 1, wherein the high-k gate dielectric region comprises a material having a gate dielectric constant greater than 8.

3. The semiconductor device according to claim 1, wherein the high-k gate dielectric region comprises a material having amorphous structure.

4. The semiconductor device of claim 1 wherein the high-k gate dielectric material includes a material selected from the group of:

tantalum, lanthanum, hafnium, aluminum, and combinations thereof.

5. The semiconductor device of claim 4 wherein the high-k gate dielectric material comprises a material selected from the group of HfO_X, HfSiO_X and HfSiO_XN_Y and combinations thereof.

6. The semiconductor device of claim 1 wherein the high-k gate dielectric material comprises AlO_X, LaO_X, HfAlO_X, and combinations thereof.

7. The semiconductor device of claim 1, wherein the gate electrode layer comprises a material selected from the group of silicon, germanium, polysilicon, metal silicide metal and combinations thereof.

8. The semiconductor device according to claim 5, wherein the counter-doping channel includes at least one dopant of a conductivity type different from the conductivity type of the substrate.

9. The semiconductor device according to claim 8, wherein the counter-doping channel is selected from a material from the group of silicon, germanium, strained silicon, strained germanium, strained silicon germanium, and combinations thereof.

10. The semiconductor device according to claim 1, wherein the counter-doping channel comprises a strained SiGe channel material.

11. The semiconductor device according to claim 10 wherein the strained SiGe channel material includes a boron dopant counter-doping.

12. The semiconductor device according to claim 1, wherein:

the sidewall spacer regions formed on the sidewalls of the gate electrode regions and high-k gate dielectric regions formed over the shallow trench isolation regions extend into the shallow trench isolation regions by a depth which is a first depth;

the sidewall spacer regions formed on the sidewalls of the gate electrode regions and high-k gate dielectric regions formed over the counter doping channel in regions other than the shallow trench isolation regions extend into the counter doping channel region by a depth that is a second depth;

wherein the first depth is different from the second depth.

13. The semiconductor device according to claim 12, wherein the ratio of the first depth to the second depth is at least 3 or greater.

14. A semiconductor integrated circuit, comprising:

a semiconductor substrate;

core region defined in the semiconductor substrate;

a peripheral region defined in the semiconductor substrate in areas other than the core region;

a first active device formed over the substrate in the core region, comprising a counter-doping channel formed on the substrate, a high-k gate dielectric formed over the substrate, and a gate conductor formed over the high-k gate dielectric;

one or more shallow trench isolation regions formed in the core region, the high-k gate dielectric and the gate conductor overlying at least one of the shallow trench isolation regions;

a second active device formed in the peripheral region and having a high-k gate dielectric and a gate conductor formed over the substrate; and

sidewalls formed over the first active device, the at least one of the shallow trench isolation regions, and the second active device, the sidewalls into the substrate or the shallow trench isolation region, respectively, and extending beneath the bottom of the high k gate dielectric.

15. The semiconductor device according to claim 14 wherein the high-k gate dielectric region comprises a material having amorphous structure.

16. The semiconductor device of claim 14 wherein the high-k gate dielectric material comprises a material selected from the group of HfO_X, HfSiO_X and HfSiO_XN_Y and combinations thereof.

17. The semiconductor device of claim 14 wherein the high-k gate dielectric material comprises a material selected from the group of AlO_X, LaO_X, HfAlO_X, and combinations thereof.

18. The semiconductor device according to claim 14, wherein the counter-doping channel region comprises a strained SiGe channel material.

19. A method for forming a semiconductor device, comprising:

forming shallow trench isolation regions into a semiconductor substrate;

forming insulator material in the shallow trench isolation regions;

forming a counter-doping channel over the semiconductor substrate;

depositing an interfacial layer over the channel;

depositing a high-k gate dielectric material over the semiconductor substrate;

depositing a gate electrode material over the high-k gate dielectric material;

forming a mask material over the gate electrode material;

patterning the mask material to define at least one insulated gate area over the semiconductor substrate;

etching the gate electrode material, the high-k gate dielectric, and the semiconductor substrate to form sidewalls of the at least one insulated gate area, the sidewalls extending into the semiconductor substrate;

forming sidewall insulators on the at least one insulated gate area, the sidewall insulators covering the sidewalls of the gate electrode and the high-k gate dielectric and extending into the semiconductor substrate to a depth beneath the bottom of the high-k gate dielectric.

20. The method of claim 19 and further comprising the steps of:

patterning the mask material to define at least one insulated gate electrode over a shallow trench isolation region in the substrate;

contemporaneously with etching the gate electrode material, the high-k gate dielectric, and the semiconductor substrate, also etching the shallow trench isolation regions to form sidewalls of the at least one insulated gate area over the shallow trench isolation region, the sidewalls extending into the shallow trench isolation region;

forming sidewall insulators on the at least one insulated gate area, the sidewall insulators covering the sidewalls of the gate electrode and the high-k gate dielectric and extending into the shallow trench isolation region to a depth beneath the bottom of the high-k gate dielectric which depth is greater than the depth that the sidewalls extend into the semiconductor substrate.