Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction

• US 7,229,902 B2
• Filed: 04/01/2005
• Issued: 06/12/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Mears, Robert J., Stephenson, Robert John
• Primary Examiner(s): Geyer; Scott B.
• Assistant Examiner(s): Ullah; Elias
• Application Number:
  US11/097,612
• Publication Number:
  US 20050170590A1
• Time in Patent Office: 802 Days
• Field of Search: 438/172, 438/191, 438/197
• US Class Current: 438/496
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

Claims

1. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some silicon atoms from opposing silicon portions of the superlattice being chemically bound together through the at least one non-semiconductor monolayer therebetween; and

forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

2. The method of claim 1, wherein the at least one pair of oppositely-doped regions comprises first and second regions in direct contact with one another.

3. The method of claim 1, wherein the at least one pair of oppositely-doped regions comprises first and second regions spaced from one another.

4. The method of claim 1, wherein the at least one pair of oppositely-doped regions are arranged in a vertical direction so that the at least one semiconductor junction extends in a lateral direction.

5. The method of claim 1, wherein the at least one pair of oppositely-doped regions are arranged in a lateral direction so that the at least one semiconductor junction extends in a vertical direction.

6. The method of claim 1 wherein each energy band-modifying layer comprises oxygen.

7. The method of claim 1, wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The method of claim 1, wherein each energy band-modifying layer is a single monolayer thick.

9. The method of claim 1 wherein each base silicon portion is less than eight monolayers thick.

10. The method of claim 1, wherein forming the superlattice further comprises forming a base semiconductor cap layer on an uppermost group of layers.

11. The method of claim 1, wherein all of the base silicon portions are a same number of monolayers thick.

12. The method of claim 1, wherein at least some of the base silicon portions are a different number of monolayers thick.

13. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon;

the energy band-modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some silicon atoms from opposing silicon portions of the superlattice being chemically bound together through the at least one oxygen monolayer therebetween; and

forming at least one pair of oppositely-doped regions in the superlattice in direct contact with one another and defining at least one semiconductor junction.

14. The method of claim 13 wherein the at least one pair of oppositely-doped regions are arranged in a vertical direction so that the at least one semiconductor junction extends in a lateral direction.

15. The method of claim 13 wherein the at least one pair of oppositely-doped regions are arranged in a lateral direction so that the at least one semiconductor junction extends in a vertical direction.

16. The method of claim 13 wherein each energy band-modifying layer is a single monolayer thick.

17. The method of claim 13 wherein each base silicon portion is less than eight monolayers thick.

18. The method of claim 13 wherein forming the superlattice further comprises forming a base semiconductor cap layer on an uppermost group of layers.

19. The method of claim 13 wherein all of the base silicon portions are a same number of monolayers thick.

20. The method of claim 13 wherein at least some of the base silicon portions are a different number of monolayers thick.

21. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some silicon atoms from opposing silicon portions of the superlattice being chemically bound together through the at least one non-semiconductor monolayer therebetween; and

forming at least one pair of oppositely-doped regions in the superlattice defining at least one semiconductor junction.

22. The method of claim 21 wherein the at least one pair of oppositely-doped regions comprises first and second regions in direct contact with one another.

23. The method of claim 21 wherein the at least one pair of oppositely-doped regions comprises first and second regions spaced from one another.

24. The method of claim 21 wherein the at least one pair of oppositely-doped regions are arranged in a vertical direction so that the at least one semiconductor junction extends in a lateral direction.

25. The method of claim 21 wherein the at least one pair of oppositely-doped regions are arranged in a lateral direction so that the at least one semiconductor junction extends in a vertical direction.

26. The method of claim 21 wherein the at least one non-semiconductor monolayer comprises oxygen.