Trench-gated MOSFET including schottky diode therein

• US 7,230,297 B2
• Filed: 05/12/2005
• Issued: 06/12/2007
• Est. Priority Date: 05/14/2004
• Status: Active Grant

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Yoshihiro, Kawaguchi, Yusuke, Nakagawa, Akio, Ono, Syotaro
• Primary Examiner(s): Dickey; Thomas L.
• Application Number:
  US11/127,224
• Publication Number:
  US 20050258479A1
• Time in Patent Office: 761 Days
• Field of Search: 257/330, 257/E29.113
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.

Claims

1. A trench-gated MIS device, comprising:

a semiconductor layer of a first conductivity type having a first surface and a second surface opposed to the first surface;

a plurality of trenches each formed in a side of the first surface of the semiconductor layer;

a plurality of gate insulating films each formed in an inner surface of each of the plural trenches;

a plurality of gate electrodes each formed inside each of the plural trenches via each of the plural gate insulating films;

a plurality of semiconductor pillar regions of a second conductivity type each formed in the side of the first surface of the semiconductor layer between adjacent ones of the plural trenches and having a depth deeper than that of the plural trenches;

a base region of the second conductivity type formed between one of the plural trenches and one of the plural semiconductor pillar regions which are adjacent to each other and having a depth shallower than that of the plural trenches;

a semiconductor region of the first conductivity type formed on the base region so as to be adjacent to one of the plural gate electrodes via one of the plural gate insulating films;

a first electrode formed above the semiconductor region; and

a second electrode formed above a side of the second surface of the semiconductor layer,

wherein at least two semiconductor pillar regions are formed in at least one position between adjacent ones of the plural trenches, the semiconductor layer of the first conductivity type is formed in a region between the at least two semiconductor pillar regions, and the first electrode is in contact with the semiconductor layer and the semiconductor region, and

wherein a total volume of impurities of the first conductivity type in the semiconductor layer and a total volume of impurities of the second conductivity type in the semiconductor pillar region in a direction along an adjacent direction of the semiconductor layer and the semiconductor pillar region are approximately equal.

2. A trench-gated MIS device as set forth in claim 1,

wherein the first electrode has a Schottky contact with the semiconductor layer.

3. A trench-gated MIS device as set forth in claim 1,

wherein the plural semiconductor pillar regions are in contact with the first electrode, and contacting portions of the plural semiconductor pillar regions with the first electrode have an impurity concentration higher than that of remaining portions of the plural semiconductor pillar regions.

4. A trench-gated MIS device as set forth in claim 1,

wherein the first electrode has an ohmic contact with the plural semiconductor pillar regions.

5. A trench-gated MIS device as set forth in claim 1,

wherein each of the plural semiconductor pillar regions is adjacent to and connected with the base region, and is connected with the first electrode electrically.

6. A trench-gated MIS device as set forth in claim 1,

wherein the plural trenches are formed to be in parallel with each other, and a formation pitch thereof is approximately uniform.

7. A trench-gated MIS device as set forth in claim 1,

wherein the plural semiconductor pillar regions are formed to be in parallel with each other, and a formation pitch thereof is approximately uniform.

8. A trench-gated MIS device, comprising:

a semiconductor layer of a first conductivity type having a first surface and a second surface opposed to the first surface;

a pillar region formed above the first surface of the semiconductor layer and having a plurality of semiconductor pillar regions of the first conductivity type and a plurality of semiconductor pillar regions of a second conductivity type, each of the plural semiconductor pillar regions of the first conductivity type and each of the plural semiconductor pillar regions of the second conductivity type being formed to be adjacent to and in contact with each other and arranged alternately;

a base region of the second conductivity type formed above the pillar region;

a semiconductor region of the first conductivity type formed above the base region;

a gate electrode formed in a trench via a gate insulating film, the trench being in contact with the base region between the semiconductor region of the first conductivity type and the semiconductor pillar region of the first conductivity type;

a first electrode formed above and connected to the semiconductor region of the first conductivity type, and being in contact with at least one of the plural semiconductor pillar regions of the first conductivity type; and

a second electrode formed above the second surface of the semiconductor layer of the first conductivity type,

wherein the plural semiconductor pillar regions of the first conductivity type and the plural semiconductor pillar regions of the second conductivity type are formed to be in parallel with each other, and a total volume of impurities of the first conductivity type in the semiconductor pillar region of the first conductivity type and a total volume of impurities of the second conductivity type in the semiconductor pillar region of the second conductivity type in a direction along an adjacent direction of the each of the plural semiconductor pillar regions of the first conductivity type and the each of the plural semiconductor pillar regions of the second conductivity type are approximately equal.

9. A trench-gated MIS device as set forth in claim 8,

wherein the first electrode has a Schottky contact with the semiconductor pillar region of the first conductivity type which is in contact with the first electrode.

10. A trench-gated MIS device as set forth in claim 9,

wherein the trench is formed in the base region formed above the semiconductor pillar region of the first conductivity type.

11. A trench-gated MIS device as set forth in claim 9,

wherein the plural semiconductor pillar regions of the second conductivity type are in contact with the first electrode, and contacting portions of the plural semiconductor pillar regions of the second conductivity type with the first electrode have an impurity concentration higher than that of remaining portions of the plural semiconductor pillar regions of the second conductivity type.

12. A trench-gated MIS device as set forth in claim 9,

wherein the first electrode has an ohmic contact with the plural semiconductor pillar regions of the second conductivity type.

13. A trench-gated MIS device as set forth in claim 9,

wherein each of the plural semiconductor pillar regions of the second conductivity type is adjacent to and connected with the base region, and is connected with the first electrode electrically.

14. A trench-gated MIS device as set forth in claim 9,

wherein no gate electrode exists in the semiconductor pillar region of the first conductivity type having the Schottky contact with the first electrode.

15. A trench-gated MIS device as set forth in claim 9,

wherein the trench is formed in plural to be in parallel with each other, and a formation pitch thereof is approximately uniform.

16. A trench-gated MIS device as set forth in claim 9,

wherein the plural semiconductor pillar regions of the first conductivity type and the plural semiconductor pillar regions of the second conductivity type are formed to be in parallel with each other, and a formation pitch of adjacent ones of the plural semiconductor pillar regions is approximately uniform.

17. A trench-gated MOSFET, comprising:

a plurality of gate electrodes each included in a trench;

a gate insulating film formed to surround each of the plural gate electrodes;

an n-type diffusion layer formed to face each of the plural gate electrodes via the gate insulating film at an upper portion of the trench;

a p-type base layer formed to face each of the plural gate electrodes via the gate insulating film at a lower portion than the upper portion of the trench;

a plurality of p-type semiconductor layers each formed to face the trench via the p-type base layer, and to reach deeper than the trench;

an n-type epitaxial layer located to face each of the plural gate electrodes via the gate insulating film at a further lower portion than the lower portion of the trench, and also located at an opposite side of some of the plural p-type semiconductor layers from a side in which the p-type base layer is located; and

a metal layer formed in contact with an upper surface of the n-type epitaxial layer at the opposite side of the some of the plural p-type semiconductor layers from the side in which the p-type base layer is located,

wherein there exists at least one of the plural p-type semiconductor layers between each one of the plural gate electrodes and another one of the plural gate electrodes adjacent to the each one of the plural gate electrodes, and

wherein a total volume of p-type impurities in the p-type semiconductor layers and a total volume of n-type impurities in the n-type epitaxial layer in a direction along an adjacent direction of the p-type semiconductor layers and the n-type epitaxial layer are approximately equal.

18. A trench-gated MOSFET as set forth in claim 17,

wherein the plural p-type semiconductor layers each has a trench structure.

19. A trench-gated MOSFET as set forth in claim 17,

wherein the trenches are formed in plural to be in parallel with each other, and a missing of the trench exists at formation pitches thereof.

20. A trench-gated MOSFET as set forth in claim 17,

wherein the trenches are formed in plural to be in parallel with each other, and formation pitches thereof are approximately uniform.

21. A trench-gated MOSFET as set forth in claim 17,

wherein the plural p-type semiconductor layers are formed by an ion implantation.

22. A trench-gated MOSFET as set forth in claim 17, wherein the plural p-type semiconductor layers are formed to reach deeper than or deep as same as a half position in a depth direction of the n-type epitaxial layer.