Semiconductor device with peripheral trench

• US 7,230,300 B2
• Filed: 08/31/2004
• Issued: 06/12/2007
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Ishida, Hiroyasu, Onda, Masahito, Kubo, Hirotoshi, Miyahara, Shouji
• Primary Examiner(s): Soward; Ida M.
• Application Number:
  US10/929,727
• Publication Number:
  US 20050073004A1
• Time in Patent Office: 1,015 Days
• Field of Search: 257328-334, 257301-305, 257/341, 257/401, 257/908
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

Conventional power MOSFETs enables prevention of an inversion in a surrounding region surrounding the outer periphery of an element region by a wide annular layer and a wide sealed metal. Since, resultantly, the area of the surrounding region is large, increase in the element region has been restrained. A semiconductor device is hereby provided which has an inversion prevention region containing an MIS (MOS) structure. The width of polysilicon for the inversion prevention region is large enough to prevent an inversion since the area of an oxide film can be increased by the depth of the trench. By this, leakage current can be reduced even though the area of the region surrounding the outer periphery of the element region is not enlarged. In addition, since the element region is enlarged, on-state resistance of the MOSFET can be reduced.

Claims

1. A semiconductor device, comprising:

an element region formed by diffusing prescribed impurities on a semiconductor substrate;

a surrounding region surrounding the element region;

a trench formed on the semiconductor substrate in the surrounding region;

an insulating film formed in the trench; and

a conductive material buried in the trench,

wherein the device is configured so that an electric potential which is applied to the substrate is also applied to the conductive material, and

a high concentration impurity region, which is in contact with the conductive material, is provided on a surface of the substrate in the surrounding region.

3. The semiconductor device according to claim 1 or 2, wherein the conductive material is polysilicon.

2. A semiconductor device, comprising:

an element region in which an insulating gate semiconductor element of a trench type is provided on a semiconductor substrate;

a surrounding region surrounding the element region;

a trench formed on the semiconductor substrate in the surrounding region;

an insulating film formed in the trench; and

a conductive material buried in the trench,

wherein the device is configured so that an electric potential which is applied to the substrate is also applied to the conductive material, and

a high concentration impurity region, which is in contact with the conductive material, is provided on a surface of the substrate in the surrounding region.

4. A semiconductor device, comprising:

a semiconductor substrate comprising a semiconductor layer formed thereon;

an element region comprising a plurality of insulating gate semiconductor elements of a trench type formed in the semiconductor layer and corresponding to an inner portion of the semiconductor substrate;

a surrounding region corresponding to a peripheral portion of the semiconductor substrate and surrounding the element region;

a trench formed in the surrounding region and filled with a conductive material, an insulating film covering an inner wall of the trench and the trench being configured so as not to operate as a transistor; and

a high concentration impurity region disposed on the substrate in the surrounding region so as to be in contact with the conductive material.