Super-junction voltage sustaining layer with alternating semiconductor and High-K dielectric regions

• US 7,230,310 B2
• Filed: 09/24/2002
• Issued: 06/12/2007
• Est. Priority Date: 11/21/2001
• Status: Expired due to Term

• Current Assignee: Tongji University
• Original Assignee: Tongji University
• Inventors: Chen, Xingbi
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Arena; Andrew O
• Application Number:
  US10/504,575
• Publication Number:
  US 20050116284A1
• Time in Patent Office: 1,722 Days
• Field of Search: 257/329, 257/487, 257/618, 257/E29.074
• US Class Current: 257/487
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device includes a device feature layer, a substrate contact layer and a voltage-sustaining layer between them. The voltage-sustaining layer includes alternating semiconductor and high permittivity dielectric regions, where each region extends from the device feature layer to the substrate contact layer. Due to the flux of charges transported dominantly through the dielectric regions, the whole voltage-sustaining layer behaves like a semiconductor having a much higher electric permittivity than that of the semiconductor itself, so that the field produced by the ionized impurities of the semiconductor regions can be much higher than that of the conventional one for sustaining the same reverse voltage, and the specific on-resistance can be lower than that of the conventional one. The use of high permittivity dielectric regions can also be applied to the charge-balance structure, i.e., to COOLMOST.

Claims

1. A semiconductor device comprising:

a substrate contact layer comprising a semiconductor of a first conductivity type, wherein said contact layer has one planar contact plane on one of its side;

a device feature layer comprising a semiconductor of a second conductivity type, wherein said device feature layer has one planar device feature plane parallel to said contact plane;

a voltage-sustaining layer for sustaining a reverse high voltage disposed between said contact plane and said device feature plane;

wherein said voltage-sustaining layer comprises a plurality of closely packed cells, each cell having only one semiconductor region of a first conductivity type and one dielectric region, a size of a cross-section of each cell parallel to said device feature plane being smaller than a distance between said contact plane and said device feature plane, and, both said semiconductor region and said dielectric region in said cell of said voltage-sustaining layer extending between said contact plane and said device feature plane;

wherein a value of an electric permittivity of said dielectric region in said cell of said voltage sustaining layer is much larger than a value of a electric permittivity of said semiconductor region in said cell of said voltage sustaining layer;

wherein in area of a cross section of said dielectric region parallel to said device feature plane is in the same order of magnitude of an area of a cross section of said semiconductor region parallel to said device feature plane;

wherein a ratio of said cross section of said dielectric region to said cross section of said semiconductor region becomes smaller with increasing distance from said device feature plane to said contact plane;

wherein the semiconductor region of each cell is fully depleted under a reverse voltage close to a breakdown voltage applied across said substrate contact layer and said device feature layer, and in most of an area of each cell, a component of an electric field parallel to said device feature plane;

wherein, under said breakdown voltage, electric fluxes generated by charges of the depleted semiconductor region of each cell beyond a distance to said device feature plane smaller than the size of said cell are terminated by said device feature plane through said dielectric region.

2. The semiconductor device according to claim 1, wherein said dielectric region has at least a part of its surface covered by a thin and low permittivity dielectric layer, wherein a thickness of said low permittivity dielectric layer is much smaller than a size of a cross-section parallel to said device feature plane of said dielectric region in said cell and the permittivity of said low permittivity dielectric layer is much smaller than said electric permittivity of said dielectric region.

3. The semiconductor device according to claim 1, wherein said substrate contact layer comprises a thick heavily doped semiconductor of a first conductivity type.

4. The semiconductor device according to claim 1, wherein said substrate contact layer comprises a thin lightly doped semiconductor of a first conductivity type formed on a thick heavily doped semiconductor of the first conductivity type.

5. The semiconductor device according to claim 1, wherein said substrate contact layer comprises a thin heavily doped semiconductor of a first conductivity type formed on a thick heavily doped semiconductor of a second conductivity type.

6. The semiconductor device of claim 1, wherein said semiconductor region in each cell of said voltage-sustaining layer comprises a drain drift region and said device feature layer comprises a source-body, a source region of a semiconductor of the first conductivity type is made on the device feature layer, a gate-insulator layer and a gate are made around an area of the device feature layer.

7. The semiconductor device of claim 1, wherein said substrate contact layer further comprises a metal.

8. The semiconductor device of claim 1, wherein said device feature layer further comprises a metal.

9. The semiconductor device of claim 1, wherein said device feature layer contact to said dielectric layer further comprises metal.