Post passivation interconnection schemes on top of the IC chips
First Claim
Patent Images
1. A circuitry component comprising:
- a semiconductor substrate;
an internal circuit in or on said semiconductor substrate;
a first intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit;
a second intra-chip driver or receiver in or on said semiconductor substrate;
a first metallization structure over said semiconductor substrate;
a passivation layer over said first metallization structure; and
a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said first intra-chip driver or receiver and said second intra-chip driver or receiver.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
57 Claims
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1. A circuitry component comprising:
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a semiconductor substrate; an internal circuit in or on said semiconductor substrate; a first intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit; a second intra-chip driver or receiver in or on said semiconductor substrate; a first metallization structure over said semiconductor substrate; a passivation layer over said first metallization structure; and a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said first intra-chip driver or receiver and said second intra-chip driver or receiver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 44, 45, 46, 47, 48)
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17. An circuitry component comprising:
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a semiconductor substrate; an internal circuit in or on said semiconductor substrate; an intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit; an off-chip driver, receiver or I/O circuit in or on said semiconductor substrate; a first metallization structure over said semiconductor substrate; an external connection connected to said off-chip driver, receiver or I/O circuit; a passivation layer over said first metallization structure; and a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said intra-chip driver or receiver and said off-chip driver, receiver or I/O circuit. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 49, 50, 51, 52, 53)
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32. A method of fabricating a circuit component, comprising:
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providing a wafer comprising a semiconductor substrate, an internal circuit in or on said semiconductor substrate, a first intra-chip driver or receiver in or on said semiconductor substrate and connected to said internal circuit, a second intra-chip driver or receiver in or on said semiconductor substrate, a first metallization structure over said semiconductor substrate, and a passivation layer, over said first metallization structure; and forming a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said first intra-chip driver or receiver and said second intra-chip driver or receiver. - View Dependent Claims (33, 34, 35, 36, 37, 54, 55)
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38. A method of fabricating a circuit component, comprising:
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providing a wafer comprising a semiconductor substrate, an internal circuit in or on said semiconductor substrate, an intra-chip driver or receiver, in or on said semiconductor substrate and connected to said internal circuit, an off-chip driver, receiver or I/O circuit in or on said semiconductor substrate, a first metallization structure over said semiconductor substrate, an external connection connected to said off-chip driver, receiver or I/O circuit, and a passivation layer over said first metallization structure; and forming a second metallization structure over said passivation layer, wherein said first and second metallization structures connect said intra-chip driver or receiver and said off-chip driver, receiver or I/O circuit. - View Dependent Claims (39, 40, 41, 42, 43, 56, 57)
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Specification