Method and circuit for cascaded pulse width modulation

• US 7,230,837 B1
• Filed: 03/27/2006
• Issued: 06/12/2007
• Est. Priority Date: 03/27/2006
• Status: Expired due to Fees

• Current Assignee: Electrical Power Research Institute, Tennessee Valley Authority (Government of the United States of America), North Carolina State University (University of North Carolina System)
• Original Assignee: Electrical Power Research Institute, Tennessee Valley Authority (Government of the United States of America), North Carolina State University (University of North Carolina System)
• Inventors: Edris, Abdel-Aty, Ingram, Michael R., Sirisukprasert, Siriroj, Huang, Qin
• Primary Examiner(s): Laxton; Gary L
• Application Number:
  US11/277,594
• Time in Patent Office: 442 Days
• Field of Search: 363/65, 363/71, 363/98, 323/283, 327/172, 327/175, 327/176, 327/182
• US Class Current: 363/71
• CPC Class Codes: H02J 3/1857 wherein such bridge converter is a multilevel converter
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters
• CPC Class Codes: H02M 7/5395 by pulse-width modulation
• CPC Class Codes: Y02E 40/20 Active power filtering [APF]

Abstract

A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, including the steps of providing a plurality of H-bridge converters per phase in the CMC circuit and utilizing a three phase duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value. The normalized duty cycle value and an output current of the CMC is used to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages. A voltage summation result and direction is obtained from a ceiling index pointer and a floor index pointer and the voltage summation result, direction from the ceiling index pointer and a floor index pointer are used to create a combined switching table for the H-bridge converters. A pulse width modulator is utilized to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.

Claims

1. A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, comprising the steps of:

(a) providing a plurality of H-bridge converters in the CMC circuit;

(b) utilizing a three phase duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value;

(c) utilizing the normalized duty cycle value and an output current of the CMC to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages;

(d) sorting the capacitor voltages to obtain a register representing sorted capacitor voltages;

(e) inputting the multi-level duty cycle voltage, the polarity of the duty cycle output voltage and the sorted capacitor voltages into an index generator;

(f) calculating a ceiling index pointer and a floor index pointer wherein the ceiling index pointer corresponds to an input ceiling duty cycle representing a number of the plurality of H-bridge converters required to generate a positive output voltage, and the floor index pointer corresponds to an input floor duty cycle representing a number of the plurality of H-bridge converters required to generate a negative output voltage;

(g) determining a voltage summation result and direction from the ceiling index pointer and a floor index pointer;

(h) utilizing the voltage summation result, direction from the ceiling index pointer and a floor index pointer to create a combined switching table for the H-bridge converters; and

(i) utilizing a pulse width modulator to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.

2. A method according to claim 1, and including the step of determining the number of levels in the CMC is determined according to the formula 2N+1, where N is the number of H-bridge converters per phase in the CMC.

3. A method according to claim 1, wherein the step of sorting the capacitor voltages comprises the step of sorting the capacitor voltages with a sorting algorithm.

4. A method according to claim 3, wherein the algorithm is a bubble sorting algorithm.

5. A method according to claim 1, wherein the CMC comprises a cascaded seven level voltage source converter (VSC).

6. A method of balancing the voltage of DC links in a cascaded multi-level converter (CMC) semiconductor circuit, comprising the steps of:

(a) providing a plurality of H-bridge converters in the CMC circuit;

(b) utilizing a three phase command multilevel duty cycle value from the main controller to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value;

(c) utilizing the normalized duty cycle value and an output current of the CMC to determine the direction and polarity of the normalized duty cycle value and a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages;

(d) sorting the capacitor voltages to obtain a register containing a plurality of indices representing sorted capacitor voltages;

(e) inputting the multi-level duty cycle voltage, the direction and polarity of the duty cycle output voltage and the sorted capacitor voltages into an index generator;

(f) calculating a ceiling index pointer and a floor index pointer wherein the ceiling index pointer corresponds to an input ceiling duty cycle representing a number of the plurality of H-bridge converters required to generate a positive output voltage, and the floor index pointer corresponds to an input floor duty cycle representing a number of the plurality of H-bridge converters required to generate a negative output voltage;

(g) determining a voltage summation result and direction from the ceiling index pointer and a floor index pointer;

(h) utilizing the voltage summation result and direction from the ceiling index pointer and a floor index pointer to create a combined switching table for the H-bridge converters; and

(i) utilizing a pulse width modulator to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.

7. A circuit for balancing the voltage of DC links in a cascaded multi-level converter (CMC), comprising:

(a) a plurality of H-bridge converters;

(b) a main controller for utilizing a three phase duty cycle value to determine a normalized duty cycle value, a ceiling duty cycle value and a floor duty cycle value;

(c) a direction and duty cycle check circuit utilizing the normalized duty cycle value and an output current of the CMC to determine the direction and polarity of a capacitor current, and utilizing the capacitor current to determine a plurality of output capacitor voltages;

(d) a sorting network circuit for sorting the capacitor voltages to obtain a register representing sorted capacitor voltages;

(e) an index generator for receiving the multi-level duty cycle voltage, the polarity of the duty cycle output voltage and the sorted capacitor voltages and calculating a ceiling index pointer and a floor index pointer wherein the ceiling index pointer corresponds to an input ceiling duty cycle representing a number of the plurality of H-bridge converters required to generate a positive output voltage, and the floor index pointer corresponds to an input floor duty cycle representing a number of the plurality of H-bridge converters required to generate a negative output voltage, determining therefrom a voltage summation result and direction from the ceiling index pointer and a floor index pointer, and utilizing the voltage summation result, direction from the ceiling index pointer and a floor index pointer to create a combined switching table for the H-bridge converters; and

(f) utilizing a pulse width modulator to balance the voltage of the DC links and thereby eliminate DC-capacitor voltage imbalance.

8. A circuit according to claim 7, wherein the circuit comprises a field programmable gate array circuit (FPGA).

9. A circuit according to claim 7, wherein the number of levels in the CMC is equal to the number obtained using the formula 2N+1, where N is the number of H-bridge converters per phase in the CMC.

10. A circuit according to claim 7, wherein the sorting network includes a sorting algorithm.

11. A circuit according to claim 10, wherein the sorting algorithm comprises a bubble sorting algorithm.

12. A circuit according to claim 7, wherein the CMC comprises a cascaded seven level voltage source converter (VSC).