Channel CODEC processor configurable for multiple wireless communications standards
First Claim
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1. A channel CODEC processor, comprising:
- an algorithm-specific kernel block operable to receive a data stream, the kernel block comprising logic tailored to perform at least one step of a channel CODEC algorithm on the data stream; and
a processor core coupled to provide configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data.
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Abstract
A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor. In particular, the reconfigurable channel CODEC processor includes processor cores and algorithm-specific kernels that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.
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Citations
37 Claims
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1. A channel CODEC processor, comprising:
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an algorithm-specific kernel block operable to receive a data stream, the kernel block comprising logic tailored to perform at least one step of a channel CODEC algorithm on the data stream; and a processor core coupled to provide configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A channel CODEC processor, comprising:
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a first algorithm-specific kernel block operable to receive a data stream, the first algorithm-specific kernel block comprising logic tailored to perform a step of a first channel CODEC algorithm on the data stream to generate a first processed data stream; a second algorithm-specific kernel block coupled to the first algorithm-specific kernel block to receive the first processed data stream, the second algorithm-specific kernel block comprising logic tailored to perform a step of a second channel CODEC algorithm on the first processed data stream to generate a second processed data stream; and a processor core coupled to provide configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel CODEC algorithm and the step of the second channel CODEC algorithm according to one of a plurality of wireless communication standards as specified by the configuration data. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A channel CODEC processor, comprising:
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an input operable to receive a data stream; a plurality of processor cores including a first processor core and a second processor core operable to process data in the data stream; a plurality of algorithm-specific kernel blocks including a first algorithm-specific kernel block and a second algorithm-specific kernel block coupled to the first processor core and the second processor core, respectively, wherein the first algorithm-specific kernel block is operable to receive first data from the first processor core and to perform at least one step of a first channel CODEC algorithm on the first data, wherein the second algorithm-specific kernel block is operable to receive second data from the second processor core and to perform at least one step of a second channel CODEC algorithm on the second data. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A communication device, comprising:
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an I/O interface operable to couple to an antenna; a modem device for modulating and demodulating data coupled to the I/O interface; and a channel CODEC processor coupled to the modem device to receive a demodulated data stream, the channel CODEC processor comprising; a first algorithm-specific kernel block operable to receive the demodulated data stream, the kernel block comprising logic tailored to perform at least one step of a channel decoding algorithm on the demodulated data stream; and a first processor core coupled to provide first configuration data to the algorithm-specific kernel block, the configuration data causing the kernel block to perform the at least one step of the channel decoding algorithm according to one of a plurality of wireless communication standards as specified by the first configuration data. - View Dependent Claims (30, 31, 32)
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33. A communication device, comprising:
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an I/O interface operable to couple to an antenna; a modem device for modulating and demodulating data coupled to the I/O interface; and a channel CODEC processor coupled to the modem device to receive a demodulated data stream, the channel CODEC processor comprising; a first algorithm-specific kernel block operable to receive the demodulated data stream, the first algorithm-specific kernel block comprising logic tailored to perform a step of a first channel decoding algorithm on the demodulated data stream to generate a first processed data stream; a second algorithm-specific kernel block coupled to the first algorithm-specific kernel block to receive the first processed data stream, the second algorithm-specific kernel block comprising logic tailored to perform a step of a second channel decoding algorithm on the first processed data stream to generate a second processed data stream; and a first processor core coupled to provide first configuration data to the algorithm-specific kernel blocks, the configuration data causing the algorithm-specific kernel blocks to perform the step of the first channel decoding algorithm and the step of the second channel decoding algorithm according to one of a plurality of wireless communication standards as specified by the first configuration data. - View Dependent Claims (34, 35, 36, 37)
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Specification