System and method for network error rate testing

• US 7,231,558 B2
• Filed: 04/24/2003
• Issued: 06/12/2007
• Est. Priority Date: 03/18/2002
• Status: Expired due to Term

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Cicchetti, Chris, Gentieu, Paul, Huynh, An, Lawson, Arthur M., Yang, Harold
• Primary Examiner(s): DILDINE JR, R STEPHEN
• Application Number:
  US10/422,456
• Publication Number:
  US 20060200708A1
• Time in Patent Office: 1,510 Days
• Field of Search: 714715-716
• US Class Current: 714/704
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 test sequence generators
• CPC Class Codes: H04L 43/06 Generation of reports
• CPC Class Codes: H04L 43/0847 Transmission error
• CPC Class Codes: H04L 43/18 Protocol analysers
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Claims

1. A bit error rate tester suitable for use in connection with a high speed network, the bit error rate tester comprising:

a first bit sequence generator;

a control logic module configured to communicate with the first bit sequence generator;

first and second memories configured and arranged for communication with the control logic module;

a transmit port configured and arranged for communication with the first bit sequence generator, the control logic module and the network;

a receive port configured and arranged for communication with the network;

a bit synchronizer configured and arranged for communication with the receive port;

a comparator configured and arranged for communication with at least one of the first and second memories.

2. The bit error rate tester as recited in claim 1, wherein the first bit sequence generator comprises a random bit sequence generator.

3. The bit error rate tester as recited in claim 1, wherein the control logic module and first and second memories collectively comprise a second bit sequence generator.

4. The bit error rate tester as recited in claim 3, wherein the second bit sequence generator comprises a non-random bit sequence generator.

5. The bit error rate tester as recited in claim 1, wherein the bit error rate testing device is suited for use with line speeds of about 10 Gigabits per second or greater.

6. The bit error rate tester as recited in claim 1, wherein the bit error rate testing device is compatible with a plurality of network protocols.

7. The bit error rate tester as recited in claim 1, wherein the bit error rate testing device is compatible with at least the 10 GE, FC, and SONET protocols.

8. The bit error rate tester as recited in claim 1, wherein the bit error rate tester is configured to operate in at least one of the following transmission modes:

raw 64-bit;

raw 66-bit;

XGMII; and

, continuous PRBS.

9. The bit error rate tester as recited in claim 1, wherein each of the receive port and the transmit port is selected from the group consisting of:

an XBI interface;

a direct serial interface; and

, a XENPAK interface.

10. The bit error rate tester as recited in claim 1, wherein the first memory comprises a ‘

Send’

RAM and the second memory comprises a ‘

Compare’

RAM.

11. The bit error rate tester as recited in claim 1, further comprising:

an encoder;

a scrambler; and

a gearbox, the encoder, scrambler and gearbox being configured and arranged for communication with the ‘

transmit’

port.

12. The bit error rate tester as recited in claim 1, further comprising:

a random bit sequence regenerator;

an encoder; and

a scrambler, the random bit sequence regenerator, the encoder and scrambler being configured and arranged for communication with the comparator.

13. The bit error rate tester as recited in claim 1, farther comprising a snoop buffer configured for at least indirect communication with at least one of:

the network; and

, the comparator.

14. The bit error rate tester as recited in claim 1, farther comprising a host interface.

15. A bit error rate tester suitable for use in connection with a high speed network, the bit error rate tester comprising:

a plurality of components configured for operation in connection with at least the 10 Gigabit Ethernet, Fibre Channel, and SONET protocols, the plurality of components including;

a first bit sequence generator;

a second bit sequence generator, comprising;

a control logic module configured to communicate with the first bit sequence generator; and

first, and second memories configured and arranged for communication with the control logic module;

a transmit port configured and arranged for communication with the first and second bit sequence generators;

a receive port configured and arranged for communication with the network;

a bit synchronizer configured and arranged for communication with the receive port;

a comparator configured and arranged for communication with the second bit sequence generator; and

a system bus that interconnects at least two of the plurality of components.

16. The bit error rate tester as recited in claim 15, wherein the first bit sequence generator comprises a placeholder/PRBS generator.

17. The bit error rate tester as recited in claim 15, wherein the second bit sequence generator comprises a non-random bit sequence generator.

18. The bit error rate tester as recited in claim 15, wherein the first memory comprises a ‘

Send’

RAM and the and second memory comprises a ‘

Receive’

RAM.

19. The bit error rate tester as recited in claim 15, wherein the first and second bit sequence generators are configured to operate in one or more of the following transmission modes:

raw 64-bit;

raw 66-bit;

XGMII; and

, continuous PRBS.

20. The bit error rate tester as recited in claim 15, wherein each of the transmit and receive ports is selected from the group consisting of:

an XBI interface;

a direct serial interface; and

, an XAUI interface.

21. The bit error rate tester as recited in claim 15, wherein the bit synchrornzer comprises:

a gearbox/bit shifter; and

a bit aligner.

22. The bit error rate tester as recited in claim 15, further comprising a statistics/counters module configured and arranged to receive output from the comparator.

23. The bit error rate tester as recited in claim 15, further comprising:

a CRC checksum module;

an encoder;

a scrambler; and

a gearbox, the CRC checksum module, encoder, scrambler and gearbox cooperating with the first bit sequence generator to substantially define a ‘

transmit’

datapath of the bit error rate tester.

24. The bit error rate tester as recited in claim 15, further comprising:

a random bit sequence regenerator;

a CRC checksum module

an encoder; and

a scrambler, the random bit sequence regenerator, CRC checksum module, encoder and scrambler cooperating with the comparator to substantially define a ‘

compare’

datapath of the bit error rate tester.

25. The bit error rate tester as recited in claim 15, further comprising:

a descrambler; and

a decoder, the descrambler and decoder cooperating with the bit synchronizer to substantially define a ‘

receive’

datapath of the bit error rate tester.

26. The bit error rate tester as recited in claim 15, further comprising a snoop buffer configured for at least indirect communication with at least one of:

the network; and

, the comparator.

27. The bit error rate tester as recited in claim 15, further comprising a host interface.

28. A method for bit error rate testing in a high speed network that includes at least one protocol-specific device which may be a retiming device or non-retiming device, the method comprising:

generating a bit sequence;

transmitting the bit sequence onto the network, the bit sequence being transmitted at a rate of 10 Gigabits per second or higher;

receiving the bit sequence from the network;

synchronizing, if necessary, the received bit sequence;

regenerating the transmitted bit sequence;

comparing the received bit sequence with the regenerated bit sequence;

identifying errors, if any, within the received bit sequence based upon the comparison of the received bit sequence with the regenerated bit sequence; and

calculating a bit error rate based upon the identified errors.

29. The method as recited in claim 28, wherein both the comparison of the received bit sequence with the regenerated bit sequence, and the identification of errors, proceed at the bit level.

30. The method as recited in claim 28, wherein at least a portion of the generated bit sequence is user-defined.

31. The method as recited in claim 28, wherein the bit sequence is generated pseudo-randomly.

32. The method as recited in claim 28, wherein the bit sequence is generated incrementally.

33. The method as recited in claim 28, wherein the bit sequence comprises arbitrary network traffic that does not necessarily conform to the network protocol.

34. The method as recited in claim 28, wherein the bit sequence conforms to the network protocol.

35. The method as recited in claim 28, wherein the generated bit sequence comprises:

data bits;

at least one idle;

a start word;

an end word; and

a checksum.

36. The method as recited in claim 28, wherein synchronizing the received bit sequence comprises bit-aligning the received bit sequence.

37. The method as recited in claim 28, wherein comparing the received bit sequence with the regenerated bit sequence comprises comparing only selected portions of the received bit sequence with selected portions of the regenerated bit sequence.

38. The method as recited in claim 28, further comprising selecting a transmission mode from the group consisting of:

raw 64-bit;

raw 66-bit;

XGMII; and

, continuous PRBS.

39. The method as recited in claim 28, further comprising performing a DC balancing of the bit sequence prior to transmission.

40. The method as recited in claim 28, further comprising detecting start and end words of the received bit sequence.

41. The method as recited in claim 40, wherein comparing the received bit sequence with the regenerated bit sequence comprises comparing only data bits between the start and end words of the received bit sequence with the data bits between the start and end words of the regenerated bit sequence.

42. The method as recited in claim 28, further comprising preventing comparison of the received bit sequence with the regenerated bit sequence when an unsynchronized bit sequence is detected.

43. The method as recited in claim 28, further comprising buffering at least a portion of the received bit sequence.

44. The method as recited in claim 43, wherein the buffering of at least a portion of the received bit sequence takes place in response to the occurrence of a triggering event.

45. The method as recited in claim 28, further comprising encoding and scrambling at least one of:

the generated bit sequence; and

, the regenerated bit sequence.

46. The method as recited in claim 28, further comprising calculating a word error rate based upon the identified errors.

47. The method as recited in claim 28, further comprising descrambling and decoding the received bit sequence.

48. The method as recited in claim 28, further comprising measuring latency of at least a portion of the high speed network.

49. A method for bit error rate testing in a high speed network that includes at least one protocol-specific device which may be a retiming device or non-retiming device, the method comprising:

generating a bit sequence, wherein at least a portion of the generated bit sequence is user-defined;

transmitting the bit sequence onto the network;

receiving the bit sequence from the network;

synchronizing, if necessary, the received bit sequence;

regenerating the transmitted bit sequence;

comparing the received bit sequence with the regenerated bit sequence;

identifying errors, if any, within the received bit sequence based upon the comparison of the received bit sequence with the regenerated bit sequence; and

calculating a bit error rate based upon the identified errors.

50. The method as recited in claim 49, wherein both the comparison of the received bit sequence with the regenerated bit sequence, and the identification of errors, proceed at the bit level.

51. The method as recited in claim 49, wherein the bit sequence is generated pseudo-randomly.

52. The method as recited in claim 49, wherein the bit sequence is generated incrementally.

53. The method as recited in claim 49, wherein the bit sequence comprises arbitrary network traffic that does not necessarily conform to the network protocol.

54. The method as recited in claim 49, wherein the bit sequence conforms to the network protocol.

55. The method as recited in claim 49, wherein the generated bit sequence comprises:

data bits;

at least one idle;

a start word;

an end word; and

a checksum.

56. The method as recited in claim 49, wherein synchronizing the received bit sequence comprises bit-aligning the received bit sequence.

57. The method as recited in claim 49, wherein comparing the received bit sequence with the regenerated bit sequence comprises comparing only selected portions of the received bit sequence with selected portions of the regenerated bit sequence.

58. The method as recited in claim 49, further comprising selecting a transmission mode from the group consisting of:

raw 64-bit;

raw 66-bit;

XGMII; and

, continuous PRBS.

59. The method as recited in claim 49, further comprising performing a DC balancing of the bit sequence prior to transmission.

60. The method as recited in claim 49, further comprising detecting start and end words of the received bit sequence.

61. The method as recited in claim 60, wherein comparing the received bit sequence with the regenerated bit sequence comprises comparing only data bits between the start and end words of the received bit sequence with the data bits between the start and end words of the regenerated bit sequence.

62. The method as recited in claim 49, further comprising preventing comparison of the received bit sequence with the regenerated bit sequence when an unsynchronized bit sequence is detected.

63. The method as recited in claim 49, further comprising buffering at least a portion of the received bit sequence.

64. The method as recited in claim 63, wherein the buffering of at least a portion of the received bit sequence takes place in response to the occurrence of a triggering event.

65. The method as recited in claim 49, further comprising encoding and scrambling at least one of:

the generated bit sequence; and

, the regenerated bit sequence.

66. The method as recited in claim 49, further comprising calculating a word error rate based upon the identified errors.

67. The method as recited in claim 49, further comprising descrambling and decoding the received bit sequence and measuring latency of at least a portion of the high speed network.