Memory module, test system and method for testing one or a plurality of memory modules

• US 7,231,562 B2
• Filed: 01/09/2004
• Issued: 06/12/2007
• Est. Priority Date: 01/11/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Beer, Peter, Ohlhoff, Carsten
• Primary Examiner(s): Decady; Albert
• Assistant Examiner(s): Radosevich; Steven D.
• Application Number:
  US10/754,455
• Publication Number:
  US 20040260987A1
• Time in Patent Office: 1,250 Days
• Field of Search: None
• US Class Current: 714/718
• CPC Class Codes: G11C 2029/0405 comprising complete test loop
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Claims

1. An integrated memory module, comprising:

a memory unit of the integrated memory module;

a self-test circuit of the integrated memory module and configured to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect; and

a test circuit of the integrated memory module and configured to;

receive defect data from at least one other memory module being tested, and

store the received defect data in the memory unit according to addresses assigned to the received defect data.

2. The integrated memory module of claim 1, wherein the test circuit is configured to:

receive defect data from a plurality of other memory modules being tested, and

store the received defect data of each of the memory modules in a corresponding memory area of the memory unit, each corresponding memory area being assigned to the respective memory module.

3. The integrated memory module of claim 1, further comprising an address assignment unit configured to generate addresses for storing the defect data.

4. The integrated memory module of claim 1, wherein the self-test circuit is configured to generate addresses for storing the defect data.

5. The integrated memory module of claim 1, further comprising a data compression unit configured to compress the received defect data in a redundancy-conforming manner prior to storage in the memory unit.

6. The integrated memory module of claim 1, wherein the test circuit is further configured to receive defect data compressed in a redundancy-conforming manner and to store them according to the assigned addresses.

7. The integrated memory module of claim 6, further comprising an address assignment unit configured to generate memory addresses for storing the compressed defect data, the memory addresses being assigned to memory areas in the other memory module being tested such that each of the compressed defect data can be assigned to a corresponding memory area in the memory unit.

8. The integrated memory module of claim 7, wherein the address assignment unit is configured to generate the memory addresses from the test addresses generated by the self-test circuit.

9. The integrated memory module of claim 7, wherein the address assignment unit comprises a shift register configured to divide an address value of the test address in accordance with a compression factor of the defect data compressed in the redundancy-conforming manner.

10. The integrated memory module of claim 1, further comprising a read-out unit configured to read out the defect data stored in the memory unit.

11. The integrated memory module of claim 1, further comprising a command decoding unit configured to operate the integrated memory module in a test mode, in which the self-test circuit tests the memory unit and outputs defect data dependent on a detected defect.

12. The integrated memory module of claim 1, further comprising a command decoding unit configured to operate the integrated memory module in a test mode, in which the test circuit receives the defect data and stores the received defect data in respectively assigned memory areas of the memory unit.

13. The integrated memory module of claim 1, further comprising a command decoding unit configured to:

operate the integrated memory module in a first test mode, in which the self-test circuit tests the memory unit and outputs defect data dependent on a detected defect; and

operate the integrated memory module in a second test mode, in which the test circuit receives the defect data from the other memory module and stores the received defect data in respectively assigned memory areas of the memory unit.

14. A test system, comprising:

a first memory module being tested, wherein outputs of the first memory module are connected to defect data lines;

a second memory module, comprising;

a memory unit;

a self-test circuit configured to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect; and

a test circuit configured to;

receive defect data from the first memory module being tested, via the defect data lines, and

store the received defect data in the memory unit according to addresses assigned to the received defect data; and

an external defect data evaluation unit configured to read out the stored defect data from the memory unit after the end of a test operation.

15. The test system of claim 14, wherein a external defect data evaluation unit is configured to start a test operation in the first memory module and the storage of the defect data in the second memory module by issue of a test start command.

16. The test system of claim 14, further comprising a plurality of the first memory module each connected to a respective one of a plurality of the second memory module;

wherein, in a plurality of test steps, each of the plurality of the first memory modules is tested successively with its respectively connected one of the first memory modules, and wherein, during the testing of each of the plurality of the first memory modules, defect data of a preceding test step is read out to the defect data evaluation unit.

17. A method for testing one or a plurality of memory modules with a testing memory module, comprising:

receiving a test start command by the plurality of memory modules signaling initiation of a self-test operation;

determining defect data in the plurality of memory modules depending on a detected defect;

transferring the defect data from the plurality of memory modules to the testing memory module;

storing the defect data in the testing memory module, the defect data being stored in addresses corresponding to memory areas from which the defect data was read in a respective one of the plurality of memory modules; and

transmitting the defect data after termination of the self-test operation and storage of all the defect data.

18. The method of claim 17, further comprising evaluation of the defect data in order to determine a repair solution.

19. The method of claim 17, further comprising compressing the defect data prior to transferring.

20. The method of claim 17, further comprising compressing the defect data in a redundancy-conforming manner prior to transferring.

21. The method of claim 17, further comprising compressing the defect data in a redundancy-conforming manner in the first memory module.