Method of manufacturing non-volatile DRAM

• US 7,232,717 B1
• Filed: 05/28/2003
• Issued: 06/19/2007
• Est. Priority Date: 05/28/2002
• Status: Expired due to Fees

• Current Assignee: O2ic, Inc.
• Original Assignee: O2ic, Inc.
• Inventors: Choi, Kyu Hyun, Li, Sheau-suey
• Primary Examiner(s): Chen; Jack
• Application Number:
  US10/447,675
• Time in Patent Office: 1,483 Days
• Field of Search: 438/200, 438/216, 438/241, 438/261, 438/266, 438/279, 438/587
• US Class Current: 438/238
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.

Claims

1. A method of making a non-volatile DRAM in a semiconductor substrate, the method comprising:

forming at least two trench isolation regions in the semiconductor substrate;

forming a first well between the two trench isolation regions;

forming a second well between the two trench isolation regions and below the first well to define a body region;

forming a first oxide layer above a first portion of the body region;

depositing a first dielectric layer above the first oxide layer;

depositing a first polysilicon layer above said first dielectric layer,

depositing a second dielectric layer above the first polysilicon layer;

depositing and patterning a first mask layer above the second dielectric layer to define a control gate of at least one non-volatile device;

etching the first oxide layer, the first dielectric layer, the first polysilicon layer and the second dielectric layer from all regions except those positioned below the first patterned mask layer;

removing the first patterned mask layer;

forming a first oxide spacer above portions of the body region and adjacent said first polysilicon layer;

forming a second oxide layer above a second portion of the body region not covered by said first oxide spacer;

forming a third oxide layer above a third portion of the body region different from the second region and not covered by said first spacer;

depositing a second polysilicon layer;

depositing and patterning a second mask layer above portions of the second polysilicon layer to define a guiding gate of the at least one non-volatile device and a gate of an associated passgate transistor;

etching the second polysilicon layer, the second oxide layer and the third oxide layers from all regions except those positioned below the second patterned mask layer to form the guiding gate of the at least one non-volatile device and the gate of the associated passgate transistor;

removing the second patterned mask layer;

depositing and patterning a third mask layer above the formed polysilicon guiding gate of the at least one non-volatile device and the polysilicon gate of the associated passgate transistor;

etching the first oxide spacer and polysilicon stringers not covered by the third mask layer;

forming LDD implant regions of the non-volatile device and the associated passgate transistor;

forming a second spacer above portions of the body region and adjacent said control gate and guiding gate of the non-volatile device as well as the gate of the associated passgate transistor;

forming source/drain regions of the non-volatile device and the associated passgate transistor;

depositing a dielectric layer over the polysilicon guiding gate of the at least one non-volatile device and the polysilicon gate of the associated passgate transistor;

forming polysilicon landing pads;

forming polysilicon vertical walls defining plates of the non-volatile DRAM capacitor.

2. The method of claim 1 wherein said first dielectric layer further includes an oxide layer and a nitride layer.

3. The method of claim 2 wherein said second dielectric layer is an oxide layer.

4. The method of claim 3 wherein said first well is a p-well and said second well is an n-well.

5. The method of claim 4 wherein said p-well is formed using at least two implant steps each having associated therewith a different energy and doping concentration.

6. The method of claim 5 wherein said n-well is formed using at least two implant steps each having associated therewith a different energy and doping concentration.

7. The method of claim 6 wherein the at least two implant steps used to form the n-well and the at least two implant steps used to form the p-well region are performed using a same mask.

8. The method of claim 7 wherein said second oxide layer has a thickness greater than the thickness of the first oxide layer.